[rescue] Perverse Question

[Jeffrey J. Nonken]

On Sat, 14 Jun 2003 20:15:53 -0700 (PDT), Francisco Javier
Mesa-Martinez wrote:
>Actually the term, and this comes from the fish's mouth (we had a
>great
>seminar with Peterson at one point) is that RISC has been
>misinterpreted
>for a long time. RISC doesn't mean few instructions in the ISA. The
>REDUCED in RISC means reduced number of cycles per instruction to
>the point
>that all integer instructions should take 1 clock cycle (after
>applying
>pipelining of course). Another thing that makes a RISC machine is a
>fixed
>instruction, both in length of bits used to encode it and length of
>cycles
>used to perfom it. This means that a simpler decoding logic can be
>achieved, and this leads to another main characteristic: NO
>microcode.

I think the Microchips qualify, then.