[rescue] Perverse Question

[Francisco Javier Mesa-Martinez]

>    While many RISC architectures are load/store, I really don't think
> that can be considered the benchmark with any degree of fairness.  (not
> that I can do much better, mind you)
>
>    I'd say "no microcode" is a big qualifying factor...many RISC
> architectures decode instructions directly rather than implementing
> them via microcode.  Pipelining too.

Actually the term, and this comes from the fish's mouth (we had a great
seminar with Peterson at one point) is that RISC has been misinterpreted
for a long time. RISC doesn't mean few instructions in the ISA. The
REDUCED in RISC means reduced number of cycles per instruction to the point
that all integer instructions should take 1 clock cycle (after applying
pipelining of course). Another thing that makes a RISC machine is a fixed
instruction, both in length of bits used to encode it and length of cycles
used to perfom it. This means that a simpler decoding logic can be
achieved, and this leads to another main characteristic: NO microcode.

to > make the distinction between RISC and "post-RISC"...where post-RISC
> architectural features are things like speculative execution and branch
> prediction.

This annoyed Peterson a big deal, meaning that speculative or reordering
or even superscalar techniques can be applied to RISC machines, since these
do not modify any of the requirements I described before.