[rescue] IBM on ebay

[dave at cca.org]

lefa at cats.ucsc.edu writes:

>RISC doesn't mean few instructions in the ISA, but rather "reduced
>instructions" in the ISA, as in the number of cycles it takes to execute
>each instruction usually by doing away with complex addressing modes. This
>is a common misconception about RISC. You can have a CISC processor with
>only 50 instructions and a RISC one with 200+ instructions. RISC implies
>simpler instructions, not a smaller ISA. In fact early bibliography
>referred to the RISC ideals as SISC (Simplified Instruction Set Computer).
>RISC came from the Berkeley that tried to not only enforce the simplified
>instruction paradigm, but also tried to enforce a 1 cycle per instruction
>rate.

People meant a lot of things when they were screwing around in the 80s.
After the market settled down and it became clear what was a win, I
think "RISC" became: "fixed length instructions & load/store". (Which
qualifies as "reduced instrcutions" as you describe above.)

Which is of course, what the CDC-6600 had going for it, back in 64.

All hail Seymour.

------ David Fischer ------- dave at cca.org ------- http://www.cca.org ------
-------- "I prefer the ridiculous to the sublime." - James Chance ---------