[rescue] IBM on ebay

[James Lockwood]

On Wed, 15 May 2002 dave at cca.org wrote:

> lefa at cats.ucsc.edu writes:
>
> >RISC doesn't mean few instructions in the ISA, but rather "reduced
> >instructions" in the ISA, as in the number of cycles it takes to execute
> >each instruction usually by doing away with complex addressing modes. This
> >is a common misconception about RISC. You can have a CISC processor with
> >only 50 instructions and a RISC one with 200+ instructions. RISC implies
> >simpler instructions, not a smaller ISA. In fact early bibliography
> >referred to the RISC ideals as SISC (Simplified Instruction Set Computer).
> >RISC came from the Berkeley that tried to not only enforce the simplified
> >instruction paradigm, but also tried to enforce a 1 cycle per instruction
> >rate.
>
> People meant a lot of things when they were screwing around in the 80s.

Agreed.

RISC was coined by David Patterson in 1980 at UCB.  At that point in time
it did mean a reduced ISA, with the goal of both a low cycle count per
instruction and a simple die that could be run at higher speeds.  RISC-I
(1982) and RISC-II (1984) were the archetypes.  32-bit, 138 registers,
330-ns cycle time with one cycle per opcode.

In the mid 80's IBM "redefined" the term to indicate a reduced instruction
cycle count, rather than a reduced ISA.  This roughly coincided with the
unveiling of ROMP.  They pushed the term "Reduced Instruction Set Cycles"
heavily.  They continued this marketing trend through the development of
the PPC and it is to this that I was referring.  I consider the POWER
string instructions highly non-RISCy as they added microcode bloat and
broke the one cycle per opcode convention.  I blame IBM heavily for the
abuse of the RISC term.

Believe me, I am not laboring under any misconceptions as to what RISC
was/is.  "RISC" in the IBM sense caused die bloat over leaner
architectures, mips was a marvel of simplicity by comparison.

> After the market settled down and it became clear what was a win, I
> think "RISC" became: "fixed length instructions & load/store". (Which
> qualifies as "reduced instrcutions" as you describe above.)

Other common features: lots of registers, no suboptimal (unaligned)
accesses, register set orthogonality.  These are all of course present in
some "CISC" archs as well.  VLIW blurs the line even more.

-James