[rescue] IBM on ebay

[Francisco Javier Mesa-Martinez]

On Tue, 14 May 2002, James Lockwood wrote:

> > >
> > > >Actually POWER evolved from the chip that was used in the DisplayWriter.
> > >
> > > What about the 801?
> >
> > Since when did POWER evolve from the 8086?
> 
> The 801 does not owe extensive heritage to the 8086 (it was an
> experimental ECL minicomputer architecture).  It draws more extensively on
> the 709 and, in spirit, the CDC 6600 (then again, so does everything
> RISC).

I wasn't talking about the 801, someone mention the displaywriter machine.
And such system was 8086 based, so I did not understand what did the 8086
have to do with the POWER.

 > Saying that POWER evolved from the 801 (via ROMP 032) is a bit of
a
> stretch.  Some things were certainly carried over (MMU) but much of the
> design was original.  RIOS (the first 6 chip POWER implementation) had 184
> instructions, hardly "RISC" by many standards.  Much of this was slimmed
> down for PowerPC and some of the more complex string operations were
> emulated.

RISC doesn't mean few instructions in the ISA, but rather "reduced
instructions" in the ISA, as in the number of cycles it takes to execute
each instruction usually by doing away with complex addressing modes. This
is a common misconception about RISC. You can have a CISC processor with
only 50 instructions and a RISC one with 200+ instructions. RISC implies
simpler instructions, not a smaller ISA. In fact early bibliography
referred to the RISC ideals as SISC (Simplified Instruction Set Computer).
RISC came from the Berkeley that tried to not only enforce the simplified
instruction paradigm, but also tried to enforce a 1 cycle per instruction
rate.