[SunHELP] (no subject)

[Bret Adams]

Looks like you have mismatched Dimms.

At 10:02 AM 1/2/02 -0800, you wrote:
>Hi,
>
>I have a Ultra 10 with 512 MB RAM, which is actually not okay. Until recently
>it detected 256MBs of RAM and did fine under this circumstances. Today it
>startet to detect 512MB and now doesn't come up any more. Any ideas beside
>getting new DIMMs?
>
>Best,
>Hannes
>
>
>Setting diag-switch? because of L1-D keyboard command.
>
>%o0 = 0000.0000.0000.2001
>
>Executing Power On SelfTest
>
>@(#) Sun Ultra 5/10 (Darwin) POST 2.2.9 (Build No. 502) 17:54 on 02/19/98
>
>CPU: UltraSPARC-LC (MHz: 301 Ecache Size:  512KB)
>
>Init POST BSS
>         Init System BSS
>NVRAM
>         NVRAM Battery Detect Test
>         NVRAM Scratch Addr Test
>         NVRAM Scratch Data Test
>DMMU TLB Tags
>         DMMU TLB Tag Access Test
>DMMU TLB RAM
>         DMMU TLB RAM Access Test
>Probe Ecache
>         Probe Ecache
>Ecache Tests
>         Ecache RAM Addr Test
>         Ecache Tag Addr Test
>All CPU Basic Tests
>         V9 Instruction Test
>         CPU Soft Trap Test
>         CPU Softint Reg and Int Test
>All Basic MMU Tests
>         DMMU Primary Context Reg Test
>         DMMU Secondary Context Reg Test
>         DMMU TSB Reg Test
>         DMMU Tag Access Reg Test
>         IMMU TSB Reg Test
>         IMMU Tag Access Reg Test
>All Basic Cache Tests
>         Dcache RAM Test
>         Icache RAM Test
>Sabre MCU Control & Status Regs Init and Tests
>         Init Sabre MCU Control & Status Regs
>                 Initializing SC registers in SabreIO
>Memory Probe and Init
>         Probe Memory
>WARNING: DIMM Mismatch Bank 0
>slot 0 upper stack :      0MB bottom stack :    128MB
>slot 1 upper stack :    128MB bottom stack :    128MB
>Memory used: upper stack :        0MB bottom stack :    256MB
>                 bank 2:   0MB
>INFO: MC0 = 0x00000000.80001192, MC1 = 0x00000000.06459acb
>         Ecache Access Test
>         Malloc Post Memory
>         Memory Addr with Ecache
>         Load Post In Memory
>         Run POST from MEM
>         .........
>loaded POST in memory
>         Map PROM/STACK/NVRAM in DMMU
>         Update Master Stack/Frame Pointers
>All FPU Basic Tests
>         FPU Regs Test
>         FPU Move Regs Test
>UPA Data Bus Line Test
>Memory Tests
>         Init Memory
>         WARNING: DIMM Mismatch Bank 0
>          128MB DIMM1
>          128MB DIMM2
>................................................................................
>................................................................................
>................................................................................
>........
>         WARNING: DIMM Mismatch Bank 0
>            0MB DIMM1
>          128MB DIMM2
>
>                 INFO:      0MB at bank 2 stack 0
>                 INFO:      0MB at bank 2 stack 1
>         ECC Memory Addr Test
>         WARNING: DIMM Mismatch Bank 0
>          128MB DIMM1
>          128MB DIMM2
>         WARNING: DIMM Mismatch Bank 0
>            0MB DIMM1
>          128MB DIMM2
>                 INFO:      0MB at bank 2 stack 0
>                 INFO:      0MB at bank 2 stack 1
>All Basic Sabre MMU Tests
>         Init Sabre
>         Interrupt Map (short) Reg Test
>         Interrupt Set/Clr Reg Test
>         Sabre IOMMU Regs Test
>         Sabre IOMMU RAM Address Test
>         Sabre IOMMU CAM Address Test
>         PBMA PCI Config Space Regs Test
>         PBMA Control/Status Reg Test
>         PBMA Diag Reg Test
>         Sabre IO Regs Test
>All Advanced CPU Tests
>         IU ASI Access Test
>         FPU ASI Access Test
>All CPU Error Reporting Tests
>         CPU Data Access Trap Test
>         CPU Addr Align Trap Test
>         DMMU Access Priv Page Test
>         DMMU Write Protected Page Test
>All Advanced Sabre IOMMU Tests
>         Init Sabre
>         Consist DMA Rd, IOMMU miss Ebus Test
>All Basic Cheerio Tests
>         Cheerio Ebus PCI Config Space Test
>         Cheerio Ethernet PCI Config Space Test
>         Cheerio Init
>All Sabre IOMMU Error Reporting Tests
>         Init Sabre
>         PIO Read, Master Abort Test
>         PIO Read, Target Abort Test
>
>
>Status of this POST run:        PASS
>manfacturing mode=OFF
>Time Stamp [hour:min:sec] 17:56:26  [month/date year] 01/02 2002
>
>
>
>
>Power On Selftest Completed
>Software Power ON0.0000.0000.0000 ffff.ffff.f00b.4448 0002.3333.0200.001b
>
>@(#) Sun Ultra 5/10 UPA/PCI  3.11 Version 9 created 1998/03/06 10:31
>Clearing E$ Tags  Done
>Clearing I/D TLBs Done
>Probing Memory Done
>MEM BASE = 0000.0000.0000.0000
>MEM SIZE = 0000.0000.1000.0000
>11-Column Mode Enabled
>MMUs ON
>Copy Done
>PC = 0000.01ff.f000.1ffc
>PC = 0000.0000.0000.2040
>Decompressing into Memory Done
>Size = 0000.0000.0006.e160
>ttya initialized
>Reset Control: BXIR:0 BPOR:0 SXIR:0 SPOR:1 POR:0
>UltraSPARC-IIi 2-2 module
>Probing Memory Bank #0 256 + 256 : 512 Megabytes
>Probing Memory Bank #2   0 +   0 :   0 Megabytes
>Data Access Error
>_______________________________________________
>SunHELP maillist  -  SunHELP at sunhelp.org
>http://www.sunhelp.org/mailman/listinfo/sunhelp