OT Linux (RE: [rescue] OT: Stuffed Proliant?)

[Joshua D Boyd]

On Sat, Dec 22, 2001 at 12:01:56AM -0500, Patrick Giagnocavo wrote:
> You get 512KB L2 cache to begin with.  OpenBSD screams fast enough on
> an AMD K6-2 450Mhz.  Will be getting an Athlon 1700XP wDDR RAM in the
> near future and will see how that goes.

Yes, but how hard do you really push the K6-2?
 
> If you want to get really picky about it, you need to include the fact
> that RISC code is generally "bigger" by 20 or 30% due to more
> instructions needed (reduce instruction set, remember.)  So 512KB
> cache on decent x86 is closer to say 630KB+ on RISC.

True, but keep in mind, for best performance on a pentium or better machine, 
you write it in a riscish manor that has nearly identical inflation factors.

For instance, you do not want to do adds to memory, so you alway mov your words
to a register before you add it, just like you ld your words on a SPARC.  Other
wise, you loose your parallelism between the two pipes.  This is covered fairly
thoroughly in Michael Abrams black book (the guy who make Quake actuall work 
decently on a Pentium instead of only PA-Risc).
 
>> pretty nice in this instance for a few reasons.  First it is possible to get
>> more cache 

> Up to 8MB on some chips/systems.

Cool.  I didn't know that sparcs went that high.  That would be really cool.  
Get a 10 proc SS1k.  It would have more L2 cache than some of my machines have
RAM.
 
>>Another problem with Intel (for some tasks) is floating point performance.  
>>When Intel quotes benchmarks saying how fast they are, they are almost always
>>using single precision.  However, almost everything uses double, which Intel
>>is no where near as good at. 
> 
> Slightly less than half the numbers quoted for single-precision.

Well, they are never twice as fast as the competition, so slightly less than
half means significantly below the competition.
 
>>Then, there is the general worthlessness of MMX and SSE. SSE2 might be decent
>>but they crippled the P4 is other ways meaning that you have to rewrite for 
>>SSE2 if you want decent performance at all.
> 
> The main boost seen from early MMX implementations was the increase in
> L2 cache size for the original Pentiums. SSE dunno.  However Intel did
> one thing right when they added hw rotate instruction, which is used
> in crypto code and makes it faster.

Yes, rotates are good for crypto, as are the 32bit registers.  I wonder how
much this really helps people running web servers as opposed to people running
distributed.net.
 
> The REAL thing I am seeing in my x86/OpenBSD systems is that the
> performance isn't balanced - I/O on stock hw is not that great until
> you buy good quality 7200 or 10K drives, good PCI enet cards, etc.




-- 
Joshua D. Boyd