[rescue] rescue Digest, Vol 129, Issue 16

[Michael Thompson]

> Date: Mon, 26 Aug 2013 21:00:49 -0700
> From: "r.stricklin" <bear at typewritten.org>
> Subject: Re: [rescue] rescue Digest, Vol 129, Issue 15
>
> On Aug 26, 2013, at 6:14 PM, Michael Thompson wrote:
>
> > The A & C rows of the J2 and the B row of the J3 was used for a
> > CPU<->Memory bus, or a graphics bus.
> > I think that the pinout of the memory bus differed between the
> processors.
>
> Yes. This bus is "optimized for DRAM timing", which could potentially
> include
> memory-mapped framebuffers.
>
> The pinout of the bus was at least the same enough for memory boards to
> interoperate between sun3, sun3x, and SPARC VME CPUs.
>
> If it matters, I am specifically interested in its use on sun2. But I'll
> take
> anything. I have a sun2 memory board that I want a clearer understanding
> of,
> in order to troubleshoot its failure mode more effectively.
>
> ok
> bear.
>

You have a 2/75?

The schematic for the 2/120 Multibus backplane is here:
http://bitsavers.trailing-edge.com/pdf/sun/sun2/800-1184-01_2-120_Backplane_Engr_Sep84.pdf
.
The memory board is here:
http://bitsavers.trailing-edge.com/pdf/sun/sun2/800-1186-01_2-120_Memory_Engr_Sep84.pdf
That shows the signals for the DRAM bus and may be close to the 3/75 bus.

-- 
Michael Thompson