[rescue] quad 486

[Joshua D. Boyd]

On Fri, Feb 21, 2003 at 10:21:47AM -0800, Brian wrote:
> > > I would be hesitant to use smp on a box with procs whose L2 cache
> > > is not on chip..

> Because then there is battling over cache access, and at a lower rate than
> the processor.  Suppose the 2 procs need something different from the
> cache, or suppose sometjing was there but now isn't because it was
> displaced by a request of the other processor.  I knew someone with a dual
> proc p166, and the way he described it to me, was that a lot of apps
> actually performed worse.

Just because Pentiums often sucked at threading on SMP doesn't mean that
on chip L2 is the answer.

Don't the UltraSPARCs use off chip L2?  I believe that the R10k also
uses off chip L2.  Yepp, here is a paper refering to that:
http://citeseer.nj.nec.com/cache/papers/cs/16180/http:zSzzSzwww.dei.unipd.itzSz~caprizSzPAPERSzSzipdps00.pdf/predicting-performance-on-smps.pdf

There are some slides from Compaq about off chip caches.  I believe in
the end they went with L3, but then L3 has the same potential problems
that you describe for L2. http://research.compaq.com/wrl/projects/Database/isca99_rac.pdf

Basically, the only thing to do is get more cache overall, and realize
that cache and cache bandwitdh need to scale as CPU count grows.  There
are more ways to do that just by putting the L2 on the CPU (which makes
Cache coherency much harder over one cache for numerous CPUs).

The only reason I can think of for on chip L2 is to reduce costs (one
package instead of two, and potentially less traces on the motherboard),
and reduce the wire length seperating the CPU die from the cache.  The
downsize is your cache size is more limited.  Thus why others look at
doing things differently.