[rescue] quad 486

[Francisco Javier Mesa-Martinez]

On Fri, 21 Feb 2003, Brian wrote:

> Because then there is battling over cache access, and at a lower rate than
> the processor.  Suppose the 2 procs need something different from the
> cache, or suppose sometjing was there but now isn't because it was
> displaced by a request of the other processor.  I knew someone with a dual
> proc p166, and the way he described it to me, was that a lot of apps
> actually performed worse.
>

I am sorry but you are a little bit missinformed. Where the L2 is on
chip or not doesn't make any difference in SMP MIMD machines, they still
have to enforce the same cache consistency... by means of snooping or any
other algorithm. Cache is cache, whether is on chip or not, cache is not
shared among different processors, as you were implying for that dual P166
(inconsistency hell otherways, and if those systems did actually share
cache among 2 procs... the designer should be shot and burried somewhere
in the woods). However what most early cheapo dual processor pentiums
were sharing was the same memory bus (between cache and chipset), which
meant that the chips were actually halving their respective memory
bandwidths (plus those caches used to be write-through, rather than
write-back which meant easier cache administration for the chipset).