[geeks] New small Intel Board

[nate at portents.com]

> Good CPU time or not, you will still have cache faults.  However,
> hopefully when thread A faults, thread Bs data will have been loaded
> into the cache in the background, so why not switch hardware contexts
> and chew on thread B while thread A's data is loaded into cache?

Right, and once you factor in things like the improved pre-fetchers along
with the integrated memory controller on Nehalem, SMT (as Intel is now
calling it) should perform pretty well.  The only info I've come across is
just the slides from the IDF:

http://www.pcper.com/article.php?aid=534&type=expert&pid=2

Nehalem is going to be four-core and eight-core, so with SMT it will show
up as 8 and 16 logical CPUs per socket, respectively.

- Nate