[geeks] New small Intel Board

[Joshua Boyd]

On Fri, Jun 06, 2008 at 04:22:28PM -0400, Alois Hammer wrote:

> > Err, hyperthreading was/is real threading.  I believe the T1/T2s just
> > double the number of contexts per core, although there could be other
> > improvements that I am not aware of.
> 
> Okay, "real" maybe wasn't the right word.  What I meant is that the
> hardware behind the extra thread was just a little unused execution unit
> time; hence an absolute maximum of ~15% real performance gain on
> intensive SMP database tests vs. turning HT off.  (And pre-Northwood HT
> was sufficiently buggered that it was either turned off by default in
> firmware, or /unalterably/ turned off in firmware, esp. in desktop
> machines.  That was even true for earlier Northwood steppings, IIRC.)  I
> was under the impression that T1/T2 hardware had significant extra
> execution units behind the extra threads, making them a little more...
> useful.

First, it is hard to say how good the idea is in general from the P4s,
even the later ones.  The Prescott and later P4s fixed up the replay
engine a bit, but not enough to really allow HT to shine (if there was
any chance of HT shining).  And my understanding is that there were
other issues with the P4 as well.  For instance, they either need to
duplicate every internal cache, or they have to flush the lengthy
pipeline to do a switch.

I haven't broken out the verilog source for in depth review, but someone
certainly could.  According to various Sun web pages, the T1 has 1
integer pipeline per core, which it uses to execute 4 threads.  BTW, the
T1 pipeline is 6 stages, versus the P4's 31 stages.  I don't recall
seeing how many stages the Atom is.

Both the T1 and the Atom put hyperthreading on a much simplified
processor, which I think will give us a better idea of how the it helps
performance.

Also, later this year, HT will be coming to Xeons again allowing us to
see how the idea holds up on a more complex chip.