[geeks] WTB: 16GB RAM dual or quad x86 system

[Patrick Giagnocavo]

On Thu, Apr 21, 2005 at 08:09:05AM -0400, James Fogg wrote:
> > >> Needed:
> > >>
> > >> 16GB RAM system
> > >> 700Mhz or higher CPUs, dual-xeon or quad xeon disk not
> > >> important at least one ethernet interface under 12U in
> > size preferred
> > >
> > > I thought 32bit systems were limited to 4G ram?
> >
> > That would be a per-CPU limit, right?
> 
> Don't think so - the limit is the address range available in a 32bit
> word. It's the big problem with large databases on Windows. Windows is
> 32bit only.

In a word, no, Intel non-64bit CPUs are not limited to 4GB RAM.  PAE
gives you 36bits of addressability.

MS's take on it:
http://www.microsoft.com/whdc/system/platform/server/PAE/pae_os.mspx

"Addressing physical memory above 4 GB requires more than the 32 bits
of address offered by the standard operating mode of Intel (32-bit)
processors. To this end, Intel introduced the 36-bit physical
addressing mode called PAE, starting with the Intel Pentium Pro
processor."

You can run the command "pagesize -a" to see which modes your
Solaris/x86 box supports.  On my Solaris 10 install on an Athlon, I
get:

# pagesize -a
4096
4194304

I asked Rich Teer (wrote the Solaris Internals book) and some other
Sun/x86 folks and the unanimous answer is that each *process* is
limited to about 3.5GB RAM, since PCI devices and the like are mapped
into the 4GB address space; however, the Solaris kernel itself will
see and use the entire amount.  Since even my lightly loaded server
has 143 processes and 590 lwps, that would not be a big limitation.

There is an API called xmemfs which allows a process to use more than
4GB RAM, but the extra RAM is essentially treated as a RAMdisk (you
mount the RAM on a loopback interface and make it available to the
process that way IIRC).

Some versions of Windows 2000 and 2003 Server also support PAE and go
up to 64GB RAM in addressability, but I don't know about (nor do I
care) any limitations on that OS.

Some earlier motherboards/chipsets had problems with PAE mode and
caching - switching to PAE mode would cause the L2 cache to do things
in a way that really affected performance.

--Patrick