[rescue] Problem with slot 0 in E4000
Michael Thompson
michael.99.thompson at gmail.com
Wed Jul 27 19:43:28 CDT 2011
I have an E4000 that used to be an E4500. I replaced the E4500
assembly above slot 0 that used to have connections to a cabinet
mounted on/off switch and SCSI connectors with an E4000 assembly that
contains a keyswitch and CDROM. If I put just one CPU board in slot 2
it works OK. If I put the same CPU board in slot 0, CPU 1 has a JTAG
problem. I have tried several CPUs and they all behave the same.
Bad backplane?
Hardware Power ON
0,0>
0,0>@(#) POST 3.9.30 2002/10/25 14:04
0,0>Copyright 2002 Sun Microsystems, Inc. All rights reserved.
0,0>
SelfTest Initializing (Diag Level 10, ENV 0000ff00) IMPL 0011 MASK 20
0,0>Board 0 CPU FPROM Test
0,0>Board 0 Basic CPU Test
0,0> Set CPU UPA Config and Init SDB Data
0,0> SRAM Mode = 22, Clock Mode = 4:1, PCON = 6fa, MCAP = 0
0,0>Board 0 MMU Enable Test
0,0> DMMU Init
0,0> IMMU Init
0,0> Mapping Selftest Enabling MMUs
0,0>Board 0 Ecache Test
0,0> Ecache Probe
0,0> Ecache Tags
0,0> Ecache Quick Verify
0,0> Ecache Init
0,0> Ecache RAM
0,0> Ecache Address Line
0,0> Configure Ecache Limit
0,0>Ecache Size = 00400000, Limited to 00400000
0,0>Board 0 FPU Functional Test
0,0> FPU Enable
0,0>Board 0 Board Master Select Test
0,0> Selecting a Board Master
0,0>Board 0 FireHose Devices Test
0,0>Board 0 Address Controller Test
0,0> AC Initialization
0,0> AC DTAG Init
0,0>Board 0 Dual Tags Test
0,0> AC DTAG Init
0,0>Board 0 FireHose Controller Test
0,0> FHC Initialization
0,0>Board 0 JTAG Test
0,0> Verify System Board Scan Ring
0,0>Board 0 Centerplane Test
0,0> Centerplane Join
0,0>Setting JTAG Master
0,0>Clear JTAG Master
0,0>Board 0 Setup Cache Size Test
0,0> Setting Up Cache Size
0,0>Board 0 System Master Select Test
0,0> Setting System Master
0,0>POST Master Selected (JTAG,CENTRAL)
0,0>Board 16 Clock Board Test
0,0> Clock Board Initialization
0,0> Clock Board Temperature Check
0,0>Board 16 Clock Board Serial Ports Test
0,0>Board 16 NVRAM Devices Test
0,0> M48T59 (TOD) Init
0,0>Board 0 System Board Probe Test
0,0> Probing all CPU/Memory BDA
0,0> Probing System Boards
0,0> Probing CPU Module JTAG Rings
0,0>ERROR: TEST=System Board Probe ,SUBTEST=Probing CPU Module JTAG
Rings ID=11.3
0,0>Component under test: Board 0 System Probe
0,0> Module is present but did not checkin MID 1
0,0>Setting System Clock Frequency
0,0> CPU Module mid 0 Checked in OK (speed code = 7)
0,0> CPU mid 1 Checked in FAILED
0,0> ******** Clock Reset - retesting
0,0>System Frequency (MHz),fcpu=336, fmod=168, fsys=84, fgen=336
0,0>
0,0>@(#) POST 3.9.30 2002/10/25 14:04
0,0>Copyright 2002 Sun Microsystems, Inc. All rights reserved.
0,0>
SelfTest Initializing (Diag Level 40, ENV 0000ff80) IMPL 0011 MASK 20
0,0>Board 0 CPU FPROM Test
0,0> CPU/Memory Board FPROM Checksum Test
0,0>Board 0 Basic CPU Test
0,0> FPU Registers and Data Path Test
0,0> Instruction Cache Tag RAM Test
0,0> Instruction Cache Instruction RAM Test
0,0> Instruction Cache Next Field RAM Test
0,0> Instruction Cache Pre-decode RAM Test
0,0> Data Cache RAM Test
0,0> Data Cache Tags Test
0,0> DMMU Registers Access Test
0,0> DMMU TLB DATA RAM Access Test
0,0> DMMU TLB TAGS Access Test
0,0> IMMU Registers Access Test
0,0> IMMU TLB DATA RAM Access Test
0,0> IMMU TLB TAGS Access Test
0,0> Set CPU UPA Config and Init SDB Data
0,0> SRAM Mode = 22, Clock Mode = 4:1, PCON = 6fa, MCAP = 0
0,0>Board 0 MMU Enable Test
0,0> DMMU Init
0,0> IMMU Init
0,0> Mapping Selftest Enabling MMUs
0,0>Board 0 Ecache Test
0,0> Ecache Probe
0,0> Ecache Tags
0,0> Ecache Quick Verify
0,0> Ecache Init
0,0> Ecache RAM
0,0> Ecache 6N RAM Pattern Test
0,0> Ecache Address Line
0,0> Configure Ecache Limit
0,0>Ecache Size = 00400000, Limited to 00400000
0,0>Board 0 FPU Functional Test
0,0> FPU Enable
0,0>Board 0 Board Master Select Test
0,0> Selecting a Board Master
0,0>Board 0 FireHose Devices Test
0,0> PROM Datapath Test
0,0> FHC CPU SRAM Test
0,0>Board 0 Address Controller Test
0,0> AC Registers Test
0,0> AC Initialization
0,0> Memory Registers Test
0,0> Memory Registers Initialization Test
0,0> AC DTAG Init
0,0>Board 0 Dual Tags Test
0,0> AC DTAG Test
0,0> AC DTAG Init
0,0>Board 0 FireHose Controller Test
0,0> FHC Initialization
0,0>Board 0 JTAG Test
0,0> Verify System Board Scan Ring
0,0>Board 0 Centerplane Test
0,0> Centerplane and Arbiter Check Test
0,0>Setting JTAG Master
0,0>Clear JTAG Master
0,0> Centerplane Join
0,0>Setting JTAG Master
0,0>Clear JTAG Master
0,0>Board 0 Setup Cache Size Test
0,0> Setting Up Cache Size
0,0>Board 0 System Master Select Test
0,0> Setting System Master
0,0>POST Master Selected (JTAG,CENTRAL)
0,0>Board 16 Clock Board Test
0,0> Clock Board Registers Test
0,0> Clock Board Initialization
0,0> Clock Board Temperature Check
0,0>Board 16 Clock Board Serial Ports Test
0,0> 85C30 Register Test
0,0> 85C30 Serial Ports Test
0,0> Keyboard Loopback
0,0> Mouse Loopback
0,0> Serial Port B Loopback
0,0> Remote Serial Port A Loopback
0,0> Remote Serial Port B Loopback
0,0>Board 16 NVRAM Devices Test
0,0> M48T59 (TOD) Init
0,0> M48T59 (TOD) Functional Part 1 Test
0,0> NVRAM(Non-Destructive) Test
0,0>Board 0 System Board Probe Test
0,0> Probing all CPU/Memory BDA
0,0> Probing System Boards
0,0> Probing CPU Module JTAG Rings
0,0>Setting System Clock Frequency
0,0> CPU Module mid 0 Checked in OK (speed code = 7)
0,0> CPU mid 1 Checked in FAILED
0,0>System Frequency (MHz),fcpu=336, fmod=168, fsys=84, fgen=336
0,0>TESTING BOARD 1
0,0>Board 1 JTAG Test
0,0> Verify System Board Scan Ring
0,0>Board 1 Centerplane Test
0,0> Centerplane Check
0,0>Board 1 Address Controller Test
0,0> AC Registers Test
0,0> AC Initialization
0,0>Setting Freq to 25MHZ
0,0> Memory Registers Test
0,0> Memory Registers Initialization Test
0,0> AC DTAG Init
0,0>Board 1 FireHose Controller Test
0,0> FHC Initialization
0,0>Board 1 NVRAM Devices Test
0,0> M48T59 (TOD) Init
0,0> M48T59 (TOD) Functional Part 1 Test
0,0> NVRAM(Non-Destructive) Test
0,0>Re-mapping to Local Device Space
0,0>Begin Central Space Serial Port access
0,0>Enable AC Control Parity
0,0>Hotplug Trigger Test
0,0>Init Counters for Hotplug
0,0>Board 0 Cross Calls Test
0,0> Cross Calls Test
0,0>WARNING Test skipped, no other CPUs present
0,0>Displaying PROM Versions
0,0>Slot 0 CPU/Memory OBP 3.2.30 2002/10/25 14:03 POST 3.9.30
2002/10/25 14:04
0,0>Slot 1 IO Type 4 FCODE 1.8.29 2001/6/18 17:26 iPOST 3.4.29
2001/6/18 17:49
0,0>Board 0 Environmental Probe Test
0,0> Environmental Probe
0,0>Checking Power Supply Configuration
0,0>Power is more than adequate, load 2 ps 4
0,0>Reconfig memory due to POR or CLOCK RESET
0,0>Reconfig memory due to DIAG_LEVEL
0,0>Board 0 Probing Memory SIMMS Test
0,0> Probe SIMMID
0,0> Populated Memory Bank Status
0,0> bd # Size Address Way Status
0,0> 0 1024 Normal
0,0>Board 0 Memory Configuration Test
0,0> Memory Interleaving
0,0> Total banks with 8MB SIMMs = 0
0,0> Total banks with 32MB SIMMs = 0
0,0> Total banks with 128MB SIMMs = 1
0,0> Total banks with 256MB SIMMs = 0
0,0> Overall memory default speed = 60ns
0,0>Do OPTIMAL INTLV
0,0> Board 0 AC rev 5 RCTIME = 0 (Tras 71)
0,0> Memory Refresh Enable
0,0>Board 0 SIMMs Test
0,0> MP Memory SIMM Clear Test
0,0> Memory Size is 1024Mbytes
0,0> CPU MID 0 clearing 00000000.00004000 to 00000000.40000000
0,0> CPU MID 0 clearing 00000000.00000000 to 00000000.00004000
0,0> Memory Walking Rows and Columns Test
0,0> MP Memory SIMM (6N RAM Patterns) Test
0,0> Memory Size is 1024Mbytes
0,0> CPU MID 0 testing 00000000.00000000 to 00000000.40000000
0,0> MP Memory SIMM (moving inverse) Test
0,0> Memory Size is 1024Mbytes
0,0> CPU MID 0 testing 00000000.00000000 to 00000000.40000000
0,0>Slave CPU Functional Tests
0,0>Board 0 Functional CPU 0 Test
0,0> Dcache Init
0,0> Dcache Enable Test
0,0> Dcache Functionality Test
0,0> Ecache Stress Test
0,0> Ecache Functional Test
0,0> CPU Dispatch (Multi-Scalar) Test
0,0> SPARC Atomic Instructions Test
0,0> SPARC Prefetch Instructions Test
0,0> CPU Softint Registers and Interrupts Test
0,0> Uni-Processor Cache Coherence Test
0,0> Branch Memory Test
0,0> SDB ECC CE Test
0,0> SDB ECC Uncorrectable Test
0,0> FPU Instruction Test
0,0>TESTING IO BOARD 1
0,0>Board 1 I/O FPROM Test
0,0> I/O Board EPROM checksum Test
0,0>@(#) iPOST 3.4.29 2001/06/18 17:49
0,0> TESTING IO BOARD 1 ASICs
0,0> TESTING SysIO Port 0
0,0>Board 1 SysIO Registers Test
0,0> SysIO Register Initialization
0,0> IOMMU Registers and RAM Test
0,0> Streaming Buffer Registers and RAM Test
0,0> SBus Control and Config Registers Test
0,0> SysIO RAM Initialization
0,0>Board 1 SysIO Functional Test
0,0> Clear Interrupt Map and State Registers
0,0> SysIO Interrupts Test
0,0> SysIO Timers/Counters Test
0,0> IOMMU Virtual Address TLB Tag Compare Test
0,0> Streaming Buffer Flush Test
0,0> DMA Merge Buffer Test
0,0> SYSIO ECC Correctable Test
0,0> SYSIO ECC UnCorrectable Test
0,0> SysIO Sbus Probe Test
0,0> SysIO Register Initialization Test
0,0> SysIO RAM Initialization Test
0,0> Clear Interrupt Map and State Registers Test
0,0>Board 1 OnBoard IO Chipset (SOC) Test
0,0> SOC SRAM Test
0,0> SOC Registers Test
0,0> SOC Interrupt Test
0,0> Clear Interrupt Map and State Registers Test
0,0> TESTING SysIO Port 1
0,0>Board 1 SysIO Registers Test
0,0> SysIO Register Initialization
0,0> IOMMU Registers and RAM Test
0,0> Streaming Buffer Registers and RAM Test
0,0> SBus Control and Config Registers Test
0,0> SysIO RAM Initialization
0,0>Board 1 SysIO Functional Test
0,0> Clear Interrupt Map and State Registers
0,0> SysIO Interrupts Test
0,0> SysIO Timers/Counters Test
0,0> IOMMU Virtual Address TLB Tag Compare Test
0,0> Streaming Buffer Flush Test
0,0> DMA Merge Buffer Test
0,0> SYSIO ECC Correctable Test
0,0> SYSIO ECC UnCorrectable Test
0,0> SysIO Sbus Probe Test
0,0> SysIO Register Initialization Test
0,0> SysIO RAM Initialization Test
0,0> Clear Interrupt Map and State Registers Test
0,0>Board 1 OnBoard IO Chipset (FEPS) Test
0,0> FAS366 Registers Test
0,0> ESP FAS366 DVMA burst mode read/write Test
0,0> FAS366 FIFO TO DMA Test
0,0> DMA TO FAS366 FIFO Test
0,0> FEPS (Ethernet) Registers Test
0,0> FEPS Ethernet(BM, DP83840, Twister) Internal Loopbacks Test
0,0> SysIO Register Initialization Test
0,0> SysIO RAM Initialization Test
0,0> Clear Interrupt Map and State Registers Test
0,0>IO BOARD 1 TESTED
0,0>SYSTEM LEVEL TESTING
0,0>Board 0 Cache Coherency Test
0,0> Multi-Processor Cache Coherence Test
0,0>WARNING Test skipped, no other CPUs present
0,0>Probing for Disk System boards
0,0>Board 0 System Interrupts Test
0,0> System Interrupts Test
0,0>Checking Power Supply Configuration
0,0>Power is more than adequate, load 2 ps 4
0,0> Check Board Present Test
0,0> Board Present Interrupt Test
0,0>POST Failed
0,0>
0,0> System Board Status
0,0>-----------------------------------------------------------------
0,0> Slot Board Status Board Type Failures
0,0>-----------------------------------------------------------------
0,0> 0 | Online/failure |+CPU/Memory | CPU1
0,0> 1 | Normal |+IO Type 4 |
0,0> 2 | Not installed | |
0,0> 3 | Not installed | |
0,0> 4 | Not installed | |
0,0> 5 | Not installed | |
0,0> 6 | Not installed | |
0,0> 7 | Not installed | |
0,0> 16 | Normal | Clock Board |
0,0>-----------------------------------------------------------------
0,0>
0,0> CPU Module Status
0,0>-----------------------------------------------------------------
0,0> MID OK Cache Speed Version
0,0>-----------------------------------------------------------------
0,0> 0 | y | 4096 | 336 | 00170011.20000507
0,0> 1 | n | 512 | 336 | 00000000.bad0dead
0,0>-----------------------------------------------------------------
0,0>System Frequency (MHz),fcpu=336, fmod=168, fsys=84, fgen=336
0,0> Populated Memory Bank Status
0,0> bd # Size Address Way Status
0,0> 0 1024 0 0 Normal
0,0>
0,0>
POST COMPLETE
0,0>Entering OBP
ttya initialized
Using POST's System Configuration
Setting up memory
fhc ac simm-status environment sram flashprom SUNW,UltraSPARC-II
SUNW,UltraSPARC
Probing UPA Slot at 2,0 sbus fhc ac environment flashprom eeprom
sbus-speed counter-timer
Probing UPA Slot at 3,0 sbus counter-timer
Probing /sbus at 2,0 at d,0 SUNW,socal sf ssd sf ssd
Probing /sbus at 2,0 at 1,0 cgsix
Probing /sbus at 2,0 at 2,0 Nothing there
Probing /sbus at 3,0 at 3,0 SUNW,hme SUNW,fas sd st
Probing /sbus at 3,0 at 0,0 SUNW,socal sf ssd sf ssd
--
Michael Thompson
--
Michael Thompson
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