[rescue] E420r problems
Dan Sikorski
me at dansikorski.com
Wed Feb 15 19:08:57 CST 2006
I have an e420r that i cannot get to boot. On a normal boot, it hangs
after initializing memory, and will not respond to a Stop-A or break on
serial console. After consulting the list archives, i tried all manner
of reseating memory modules and the riser card. Some googling for my
errors during a boot with max diag turned on led me to this:
http://supportforum.sun.com/hardware/index.php?t=msg&th=1736&rid=0#msg_6154
I've pasted my boot messages below, but before i buy a new system board
for this, i figured i would consult the list. If i do need a board,
does anyone have an extra that they're looking to get rid of?
Otherwise, it looks like i can get one here:
http://cgi.ebay.com/SUN-E420R-ULTRA-80-MOTHERBOARD-501-5168_W0QQitemZ5816653492QQcategoryZ20328QQssPageNameZWDVWQQrdZ1QQcmdZViewItem
Can anyone comment on the seller? (Calling Pat Finnigan! it looks like
you bought two of those from that seller last year.)
-Dan Sikorski
Hardware Power ON
Master CPU : 0000.0000.0055.11a0
Slave CPU : 0000.0001.0055.11a0
Slave CPU : 0000.0002.0055.11a0
Slave CPU : 0000.0003.0055.11a0
Master E$ : 0000.0000.0040.0000
Slave E$ : 0000.0000.0040.0000
Slave E$ : 0000.0000.0040.0000
Slave E$ : 0000.0000.0040.0000
Button Power ON
Master CPU : 0000.0000.0055.11a0
Slave CPU : 0000.0001.0055.11a0
Slave CPU : 0000.0002.0055.11a0
Slave CPU : 0000.0003.0055.11a0
Master E$ : 0000.0000.0040.0000
Slave E$ : 0000.0000.0040.0000
Slave E$ : 0000.0000.0040.0000
Slave E$ : 0000.0000.0040.0000
Probing keyboard Done
Executing Power On SelfTest
0>
0>@(#) Sun Ultra 80(UltraSPARC-II 4-way) UPA/PCI POST 1.2.7 05/24/1999
05:33 PM
0>INFO: Processor 0 is master. CPU 450 MHz. 4304KB Ecache.
0>
0> <00> Init System BSS
0> <00> NVRAM Battery Detect Test
0> <00> NVRAM Scratch Addr Test
0> <00> DMMU TLB Tag Access Test
0> <00> DMMU TLB RAM Access Test
0> <00> IMMU TLB Tag Access Test
0> <00> IMMU TLB RAM Access Test
0> <00> Probe Ecache
0> <00> Ecache RAM Addr Test
0> <00> Ecache Tag Addr Test
0> <00> Ecache Tag Test
0> <00> Invalidate Ecache Tags
0>INFO: Processor 1 - UltraSPARC-II.
0>INFO: Processor 2 - UltraSPARC-II.
0>INFO: Processor 3 - UltraSPARC-II.
0> <00> Init SC Regs
0> <00> SC Address Reg Test
0> <00> SC Reg Index Test
0> <00> SC Regs Test
0> <00> SC Dtag RAM Addr Test
0> <00> SC Cache Size Init
0> <00> SC Dtag RAM Data Test
0> <00> SC Dtag Init
0> <00> Probe Memory
0>INFO: 1024MB Bank 0
0>INFO: 1024MB Bank 1
0>INFO: 1024MB Bank 2
0>INFO: 1024MB Bank 3
0> <00> Malloc Post Memory
0> <00> Init Post Memory
0> <00> Post Memory Addr Test
0> <00> Map PROM/STACK/NVRAM in DMMU
0> <00> Memory Stack Test
3> <00> DMMU TLB Tag Access Test
1> <00> DMMU TLB Tag Access Test
2> <00> DMMU TLB Tag Access Test
3> <00> DMMU TLB RAM Access Test
2> <00> DMMU TLB RAM Access Test
1> <00> DMMU TLB RAM Access Test
3> <00> IMMU TLB Tag Access Test
2> <00> IMMU TLB Tag Access Test
1> <00> IMMU TLB Tag Access Test
3> <00> IMMU TLB RAM Access Test
2> <00> IMMU TLB RAM Access Test
1> <00> IMMU TLB RAM Access Test
3> <00> Probe Ecache
2> <00> Probe Ecache
3> <00> Ecache RAM Addr Test
2> <00> Ecache RAM Addr Test
1> <00> Probe Ecache
3> <00> Ecache Tag Addr Test
2> <00> Ecache Tag Addr Test
1> <00> Ecache RAM Addr Test
3> <00> Ecache Tag Test
2> <00> Ecache Tag Test
1> <00> Ecache Tag Addr Test
1> <00> Ecache Tag Test
3> <00> Invalidate Ecache Tags
2> <00> Invalidate Ecache Tags
1> <00> Invalidate Ecache Tags
3> <00> Map PROM/STACK/NVRAM in DMMU
2> <00> Map PROM/STACK/NVRAM in DMMU
3> <00> Update Slave Stack/Frame Ptrs
1> <00> Map PROM/STACK/NVRAM in DMMU
2> <00> Update Slave Stack/Frame Ptrs
0> <00> DMMU Hit/Miss Test
1> <00> Update Slave Stack/Frame Ptrs
0> <00> IMMU Hit/Miss Test
0> <00> DMMU Little Endian Test
0> <00> IU ASI Access Test
0> <00> FPU ASI Access Test
3> <00> DMMU Hit/Miss Test
1> <00> DMMU Hit/Miss Test
2> <00> DMMU Hit/Miss Test
3> <00> IMMU Hit/Miss Test
1> <00> IMMU Hit/Miss Test
2> <00> IMMU Hit/Miss Test
3> <00> DMMU Little Endian Test
1> <00> DMMU Little Endian Test
2> <00> DMMU Little Endian Test
3> <00> IU ASI Access Test
1> <00> IU ASI Access Test
2> <00> IU ASI Access Test
3> <00> FPU ASI Access Test
1> <00> FPU ASI Access Test
2> <00> FPU ASI Access Test
3> <00> Dcache RAM Test
2> <00> Dcache RAM Test
1> <00> Dcache RAM Test
3> <00> Dcache Tag Test
2> <00> Dcache Tag Test
1> <00> Dcache Tag Test
3> <00> Icache RAM Test
2> <00> Icache RAM Test
1> <00> Icache RAM Test
3> <00> Icache Tag Test
2> <00> Icache Tag Test
1> <00> Icache Tag Test
3> <00> Icache Next Test
2> <00> Icache Next Test
1> <00> Icache Next Test
3> <00> Icache Predecode Test
2> <00> Icache Predecode Test
1> <00> Icache Predecode Test
0> <1f> Init Psycho
0> <1f> PIO Read Error, Master Abort Test
0> <1f> PIO Read Error, Target Abort Test
0> <1f> PIO Write Error, Master Abort Test
0> <1f> PIO Write Error, Target Abort Test
0> <1f> Timer Increment Test
0> <1f> Init Psycho
0> <1f> Pass-Thru DMA UE ECC Rd Err Lpbk Test
0> <00> V9 Instruction Test
0> <00> CPU Tick and Tick Compare Reg Test
0> <00> CPU Soft Trap Test
0> <00> CPU Softint Reg and Int Test
3> <00> V9 Instruction Test
1> <00> V9 Instruction Test
2> <00> V9 Instruction Test
3> <00> CPU Tick and Tick Compare Reg Test
1> <00> CPU Tick and Tick Compare Reg Test
2> <00> CPU Tick and Tick Compare Reg Test
0> <00> Copy Post to Memory
0> <00> Ecache Thrash Test
0> <00> ECC Mem Addr Clear
0> <00> Memory Addr w/ Ecache Test
0>INFO: 1024MB Bank 0
0>INFO: 1024MB Bank 1
0>INFO: 1024MB Bank 2
0>INFO: 1024MB Bank 3
0> <00> Block Memory Addr Test
0>INFO: 1024MB Bank 0
0>INFO: 1024MB Bank 1
0>INFO: 1024MB Bank 2
0>INFO: 1024MB Bank 3
0> <00> ECC Memory Addr Test
0>INFO: 1024MB Bank 0
0>INFO: 1024MB Bank 1
0>INFO: 1024MB Bank 2
0>INFO: 1024MB Bank 3
0> <00> Memory Status Test
0>INFO: 1024MB Bank 0
0>INFO: 1024MB Bank 1
0>INFO: 1024MB Bank 2
0>INFO: 1024MB Bank 3
0> <00> FPU Regs Test
0> <00> FPU Move Regs Test
0> <00> FPU State Reg Test
0> <00> FPU Functional Test
0> <00> FPU Trap Test
0> <00> DMMU Primary Context Reg Test
0> <00> DMMU Secondary Context Reg Test
0> <00> DMMU TSB Reg Test
0> <00> DMMU Tag Access Reg Test
0> <00> DMMU VA Watchpoint Reg Test
0> <00> DMMU PA Watchpoint Reg Test
0> <00> IMMU TSB Reg Test
0> <00> IMMU Tag Access Reg Test
0> <00> DMMU TLB Tag Access Test
0> <00> DMMU TLB RAM Access Test
0> <00> Dcache RAM Test
0> <00> Dcache Tag Test
0> <00> Icache RAM Test
0> <00> Icache Tag Test
0> <00> Icache Next Test
0> <00> Icache Predecode Test
2> <00> FPU Regs Test
3> <00> FPU Regs Test
1> <00> FPU Regs Test
1> <00> FPU Move Regs Test
2> <00> FPU Move Regs Test
3> <00> FPU Move Regs Test
1> <00> FPU State Reg Test
2> <00> FPU State Reg Test
3> <00> FPU State Reg Test
1> <00> FPU Functional Test
2> <00> FPU Functional Test
3> <00> FPU Functional Test
1> <00> FPU Trap Test
2> <00> FPU Trap Test
3> <00> FPU Trap Test
2> <00> DMMU Primary Context Reg Test
3> <00> DMMU Primary Context Reg Test
1> <00> DMMU Primary Context Reg Test
2> <00> DMMU Secondary Context Reg Test
3> <00> DMMU Secondary Context Reg Test
1> <00> DMMU Secondary Context Reg Test
2> <00> DMMU TSB Reg Test
3> <00> DMMU TSB Reg Test
1> <00> DMMU TSB Reg Test
2> <00> DMMU Tag Access Reg Test
3> <00> DMMU Tag Access Reg Test
1> <00> DMMU Tag Access Reg Test
2> <00> DMMU VA Watchpoint Reg Test
3> <00> DMMU VA Watchpoint Reg Test
1> <00> DMMU VA Watchpoint Reg Test
2> <00> DMMU PA Watchpoint Reg Test
3> <00> DMMU PA Watchpoint Reg Test
1> <00> DMMU PA Watchpoint Reg Test
2> <00> IMMU TSB Reg Test
3> <00> IMMU TSB Reg Test
1> <00> IMMU TSB Reg Test
2> <00> IMMU Tag Access Reg Test
3> <00> IMMU Tag Access Reg Test
1> <00> IMMU Tag Access Reg Test
2> <00> DMMU TLB Tag Access Test
3> <00> DMMU TLB Tag Access Test
1> <00> DMMU TLB Tag Access Test
2> <00> DMMU TLB RAM Access Test
3> <00> DMMU TLB RAM Access Test
1> <00> DMMU TLB RAM Access Test
0> <00> CPU Addr Align Trap Test
0> <00> DMMU Access Priv Page Test
0> <00> DMMU Write Protected Page Test
0> <1f> Init Psycho
0> <1f> Psycho Cntl and UPA Reg Test
0> <1f> Psycho DMA Scoreboard Reg Test
0> <1f> Psycho Perf Cntl Reg Test
0> <1f> PIO Decoder and BCT Test
0> <1f> PCI Byte Enable Test
0> <1f> Counter/Timer Limit Regs Test
0> <1f> Timer Reload Test
0> <1f> Timer Periodic Test
0> <1f> Mondo Int Map (short) Reg Test
0> <1f> Mondo Int Set/Clr Reg Test
0> <1f> Psycho IOMMU Regs Test
0> <1f> Psycho IOMMU RAM NTA Test
0> <1f> Psycho IOMMU CAM NTA Test
0> <1f> Psycho IOMMU RAM Address Test
0> <1f> Psycho IOMMU CAM Address Test
0> <1f> IOMMU TLB Compare Test
0> <1f> IOMMU TLB Flush Test
0> <1f> Stream Buff A Control Reg Test
0> <1f> Psycho ScacheA Page Tag Addr Test
0> <1f> Psycho ScacheA Line Tag Addr Test
0> <1f> Psycho ScacheA RAM Addr Test
0> <1f> Psycho ScacheA Page Tag NTA Test
0> <1f> Psycho ScacheA Line Tag NTA Test
0> <1f> Psycho ScacheA Error Status NTA Test
0> <1f> Psycho ScacheA RAM NTA Test
0> <1f> Stream Buff B Control Reg Test
0> <1f> Psycho ScacheB Page Tag Addr Test
0> <1f> Psycho ScacheB Line Tag Addr Test
0> <1f> Psycho ScacheB RAM Addr Test
0> <1f> Psycho ScacheB Page Tag NTA Test
0> <1f> Psycho ScacheB Line Tag NTA Test
0> <1f> Psycho ScacheB Error Status NTA Test
0> <1f> Psycho ScacheB RAM NTA Test
0> <1f> PBMA PCI Config Space Regs Test
0> <1f> PBMA Control/Status Reg Test
0> <1f> PBMA Diag Reg Test
0> <1f> PBMB PCI Config Space Regs Test
0> <1f> PBMB Control/Status Reg Test
0> <1f> PBMB Diag Reg Test
0> <1f> Init Psycho
0> <1f> Pri CE ECC Error Test
0> <1f> Pri UE ECC Error Test
0> <1f> Pri 2 bit w/ bit hole UE ECC Err Test
0> <1f> Pri 3 bit UE ECC Err Test
0> <1f> Streaming DMA UE ECC Rd Err Ebus Test
0> <1f> Streaming DMA CE ECC Rd Err Ebus Test
0> <1f> Streaming DMA CE ECC Rd Err Lpbk Test
0> <1f> Consistent DMA UE ECC Rd Error Ebus Test
0> <1f> Consistent DMA UE ECC R/M/W Err Ebus Test
0> <1f> Consistent DMA UE ECC R/M/W Err Lpbk Test
0> <1f> Consistent DMA CE ECC Rd Err Ebus Test
0>STATUS =FAILED
0>TEST =Consistent DMA CE ECC Rd Err Ebus
TTF =0
PASSES =1
ERRORS =1
SUSPECT=Psycho (Functional) U1701
0>MESSAGE=Psycho ECC Async Fault Stat Reg
addr 000001fe.00000030
exp 00000000.ff800000
obs 48000000.ff800000
0>STATUS =FAILED
0>TEST =Consistent DMA CE ECC Rd Err Ebus
TTF =0
PASSES =1
ERRORS =1
SUSPECT=Psycho (Functional) U1701
0>MESSAGE=PCI Config Status Reg
addr 000001fe.01000006
exp 0280
obs 0a80
0>STATUS =FAILED
0>TEST =Consistent DMA CE ECC Rd Err Ebus
TTF =0
PASSES =1
ERRORS =1
SUSPECT=Psycho (Functional) U1701
0>MESSAGE=Psycho ECC Async Fault Stat Reg
addr 000001fe.00000030
exp 00000000.ff800000
obs 48000000.ff800000
0>STATUS =FAILED
0>TEST =Consistent DMA CE ECC Rd Err Ebus
TTF =0
PASSES =1
ERRORS =1
SUSPECT=Psycho (Functional) U1701
0>MESSAGE=PCI Config Status Reg
addr 000001fe.01000006
exp 0280
obs 0a80
0>STATUS =FAILED
0>TEST =Consistent DMA CE ECC Rd Err Ebus
TTF =0
PASSES =1
ERRORS =1
SUSPECT=Psycho (Functional) U1701
0>MESSAGE=Psycho ECC Async Fault Stat Reg
addr 000001fe.00000030
exp 00000000.ff800000
obs 48000000.ff800000
0>STATUS =FAILED
0>TEST =Consistent DMA CE ECC Rd Err Ebus
TTF =0
PASSES =1
ERRORS =1
SUSPECT=Psycho (Functional) U1701
0>MESSAGE=PCI Config Status Reg
addr 000001fe.01000006
exp 0280
obs 0a80
0>STATUS =FAILED
0>TEST =Consistent DMA CE ECC Rd Err Ebus
TTF =0
PASSES =1
ERRORS =1
SUSPECT=Psycho (Functional) U1701
0>MESSAGE=Psycho ECC Async Fault Stat Reg
addr 000001fe.00000030
exp 00000000.ff800000
obs 48000000.ff800000
0>STATUS =FAILED
0>TEST =Consistent DMA CE ECC Rd Err Ebus
TTF =0
PASSES =1
ERRORS =1
SUSPECT=Psycho (Functional) U1701
0>MESSAGE=PCI Config Status Reg
addr 000001fe.01000006
exp 0280
obs 0a80
0>STATUS =FAILED
0>TEST =Consistent DMA CE ECC Rd Err Ebus
TTF =0
PASSES =1
ERRORS =1
SUSPECT=Psycho (Functional) U1701
0>MESSAGE=Psycho ECC Async Fault Stat Reg
addr 000001fe.00000030
exp 00000000.ff800000
obs 48000000.ff800000
0>STATUS =FAILED
0>TEST =Consistent DMA CE ECC Rd Err Ebus
TTF =0
PASSES =1
ERRORS =1
SUSPECT=Psycho (Functional) U1701
0>MESSAGE=PCI Config Status Reg
addr 000001fe.01000006
exp 0280
obs 0a80
0>STATUS =FAILED
0>TEST =Consistent DMA CE ECC Rd Err Ebus
TTF =0
PASSES =1
ERRORS =1
SUSPECT=Psycho (Functional) U1701
0>MESSAGE=Psycho ECC Async Fault Stat Reg
addr 000001fe.00000030
exp 00000000.ff800000
obs 48000000.ff800000
0>STATUS =FAILED
0>TEST =Consistent DMA CE ECC Rd Err Ebus
TTF =0
PASSES =1
ERRORS =1
SUSPECT=Psycho (Functional) U1701
0>MESSAGE=PCI Config Status Reg
addr 000001fe.01000006
exp 0280
obs 0a80
0>STATUS =FAILED
0>TEST =Consistent DMA CE ECC Rd Err Ebus
TTF =0
PASSES =1
ERRORS =1
SUSPECT=Psycho (Functional) U1701
0>MESSAGE=Psycho ECC Async Fault Stat Reg
addr 000001fe.00000030
exp 00000000.ff800000
obs 48000000.ff800000
0>STATUS =FAILED
0>TEST =Consistent DMA CE ECC Rd Err Ebus
TTF =0
PASSES =1
ERRORS =1
SUSPECT=Psycho (Functional) U1701
0>MESSAGE=PCI Config Status Reg
addr 000001fe.01000006
exp 0280
obs 0a80
0>STATUS =FAILED
0>TEST =Consistent DMA CE ECC Rd Err Ebus
TTF =0
PASSES =1
ERRORS =1
SUSPECT=Psycho (Functional) U1701
0>MESSAGE=Psycho ECC Async Fault Stat Reg
addr 000001fe.00000030
exp 00000000.ff800000
obs 48000000.ff800000
0>STATUS =FAILED
0>TEST =Consistent DMA CE ECC Rd Err Ebus
TTF =0
PASSES =1
ERRORS =1
SUSPECT=Psycho (Functional) U1701
0>MESSAGE=PCI Config Status Reg
addr 000001fe.01000006
exp 0280
obs 0a80
0>STATUS =FAILED
0>TEST =Consistent DMA CE ECC Rd Err Ebus
TTF =0
PASSES =1
ERRORS =1
SUSPECT=Psycho (Functional) U1701
0>MESSAGE=Psycho ECC Async Fault Stat Reg
addr 000001fe.00000030
exp 00000000.ff800000
obs 48000000.ff800000
0>STATUS =FAILED
0>TEST =Consistent DMA CE ECC Rd Err Ebus
TTF =0
PASSES =1
ERRORS =1
SUSPECT=Psycho (Functional) U1701
0>MESSAGE=PCI Config Status Reg
addr 000001fe.01000006
exp 0280
obs 0a80
0>STATUS =FAILED
0>TEST =Consistent DMA CE ECC Rd Err Ebus
TTF =0
PASSES =1
ERRORS =1
SUSPECT=Psycho (Functional) U1701
0>MESSAGE=Psycho ECC Async Fault Stat Reg
addr 000001fe.00000030
exp 00000000.ff800000
obs 48000000.ff800000
0>STATUS =FAILED
0>TEST =Consistent DMA CE ECC Rd Err Ebus
TTF =0
PASSES =1
ERRORS =1
SUSPECT=Psycho (Functional) U1701
0>MESSAGE=PCI Config Status Reg
addr 000001fe.01000006
exp 0280
obs 0a80
0>STATUS =FAILED
0>TEST =Consistent DMA CE ECC Rd Err Ebus
TTF =0
PASSES =1
ERRORS =1
SUSPECT=Psycho (Functional) U1701
0>MESSAGE=Psycho ECC Async Fault Stat Reg
addr 000001fe.00000030
exp 00000000.ff800000
obs 48000000.ff800000
0>STATUS =FAILED
0>TEST =Consistent DMA CE ECC Rd Err Ebus
TTF =0
PASSES =1
ERRORS =1
SUSPECT=Psycho (Functional) U1701
0>MESSAGE=PCI Config Status Reg
addr 000001fe.01000006
exp 0280
obs 0a80
0>STATUS =FAILED
0>TEST =Consistent DMA CE ECC Rd Err Ebus
TTF =0
PASSES =1
ERRORS =1
SUSPECT=Psycho (Functional) U1701
0>MESSAGE=Psycho ECC Async Fault Stat Reg
addr 000001fe.00000030
exp 00000000.ff800000
obs 48000000.ff800000
0>STATUS =FAILED
0>TEST =Consistent DMA CE ECC Rd Err Ebus
TTF =0
PASSES =1
ERRORS =1
SUSPECT=Psycho (Functional) U1701
0>MESSAGE=PCI Config Status Reg
addr 000001fe.01000006
exp 0280
obs 0a80
0>STATUS =FAILED
0>TEST =Consistent DMA CE ECC Rd Err Ebus
TTF =0
PASSES =1
ERRORS =1
SUSPECT=Psycho (Functional) U1701
0>MESSAGE=Psycho ECC Async Fault Stat Reg
addr 000001fe.00000030
exp 00000000.ff800000
obs 48000000.ff800000
0>STATUS =FAILED
0>TEST =Consistent DMA CE ECC Rd Err Ebus
TTF =0
PASSES =1
ERRORS =1
SUSPECT=Psycho (Functional) U1701
0>MESSAGE=PCI Config Status Reg
addr 000001fe.01000006
exp 0280
obs 0a80
0>STATUS =FAILED
0>TEST =Consistent DMA CE ECC Rd Err Ebus
TTF =0
PASSES =1
ERRORS =1
SUSPECT=Psycho (Functional) U1701
0>MESSAGE=Psycho ECC Async Fault Stat Reg
addr 000001fe.00000030
exp 00000000.ff800000
obs 48000000.ff800000
0>STATUS =FAILED
0>TEST =Consistent DMA CE ECC Rd Err Ebus
TTF =0
PASSES =1
ERRORS =1
SUSPECT=Psycho (Functional) U1701
0>MESSAGE=PCI Config Status Reg
addr 000001fe.01000006
exp 0280
obs 0a80
0>STATUS =FAILED
0>TEST =Consistent DMA CE ECC Rd Err Ebus
TTF =0
PASSES =1
ERRORS =1
SUSPECT=Psycho (Functional) U1701
0>MESSAGE=Psycho ECC Async Fault Stat Reg
addr 000001fe.00000030
exp 00000000.ff800000
obs 48000000.ff800000
0>STATUS =FAILED
0>TEST =Consistent DMA CE ECC Rd Err Ebus
TTF =0
PASSES =1
ERRORS =1
SUSPECT=Psycho (Functional) U1701
0>MESSAGE=PCI Config Status Reg
addr 000001fe.01000006
exp 0280
obs 0a80
0>STATUS =FAILED
0>TEST =Consistent DMA CE ECC Rd Err Ebus
TTF =0
PASSES =1
ERRORS =1
SUSPECT=Psycho (Functional) U1701
0>MESSAGE=Psycho ECC Async Fault Stat Reg
addr 000001fe.00000030
exp 00000000.ff800000
obs 48000000.ff800000
0>STATUS =FAILED
0>TEST =Consistent DMA CE ECC Rd Err Ebus
TTF =0
PASSES =1
ERRORS =1
SUSPECT=Psycho (Functional) U1701
0>MESSAGE=PCI Config Status Reg
addr 000001fe.01000006
exp 0280
obs 0a80
0> <1f> Init Psycho
0> <1f> Mondo Generate Interrupt Test
0> <1f> Timer Interrupt Test
0> <1f> Timer Interrupt w/ periodic Test
0> <1f> Psycho Stream Buff A Flush Sync Test
0> <1f> Psycho Stream Buff B Flush Sync Test
0> <1f> Psycho Stream Buff A Flush Invalidate Test
0> <1f> Psycho Stream Buff B Flush Invalidate Test
0> <1f> Psycho Merge Buffer w/ Scache A Test
0> <1f> Psycho Merge Buffer w/ Scache B Test
0> <1f> Consist DMA Rd, IOMMU miss Ebus Test
0> <1f> Consist DMA Rd, IOMMU miss Lpbk Test
0>STATUS =FAILED
0>TEST =Consist DMA Rd, IOMMU miss Lpbk
TTF =0
PASSES =1
ERRORS =1
SUSPECT=Psycho (Functional) U1701
0>MESSAGE=Psycho ECC Async Fault Stat Reg
addr 000001fe.00000040
exp 00620000.ff800000
obs 48620000.ff800000
0> <00> UltraSPARC-2 Prefetch Instructions Test
0> <00> Test 0: prefetch_mr
0> Unexpected event occurred - Trap
0> tl tt tstate tpc tnpc
0> 01 63 00000044.80001603 ffffffff.f00996c4 ffffffff.f00996c8
0> AFSR 00000000.00100000
0> AFAR 00000000.00099930
0> (CE) Correctable ECC Error
0> SDBH = 00000000.00000003 SDBL = 00000000.00000162
0>
Failing address = 00000000.00000000
0>TT(0x63) Corrected ECC Error
Power On Selftest Completed
Status = 0000.0000.0000.0001 ffff.ffff.f00b.d888
ff9f.ffff.0b91.1111\uffff
Software Power ON
Master CPU : 0000.0000.0055.11a0
Slave CPU : 0000.0001.0055.11a0
Slave CPU : 0000.0002.0055.11a0
Slave CPU : 0000.0003.0055.11a0
Master E$ : 0000.0000.0040.0000
Slave E$ : 0000.0000.0040.0000
Slave E$ : 0000.0000.0040.0000
Slave E$ : 0000.0000.0040.0000
@(#) UPA/PCI 3.23 Version 0 created 1999/06/30 13:53
Clearing DTAGS Done
Probing Memory
CONFIG = 0000.0000.1010.1010
MEM BASE = 0000.0000.0000.0000
MEM SIZE = 0000.0001.0000.0000
MMUs ON
Copy Done
PC = 0000.01ff.f000.2a50
PC = 0000.0000.0000.2a94
Decompressing into Memory Done
Size = 0000.0000.0006.ef90
ttya initialized
SC Control: EWP:0 IAP:0 FATAL:0 WAKEUP:0 BXIR:0 BPOR:0 SXIR:0 SPOR:1 POR:0
Probing Memory Bank #0 1 1 1 1 : 4 Gigabytes
Probing Floppy: No drives detected
Probing EBUS Nothing there
Probing UPA Slot at 1e,0 Nothing there
Probing UPA Slot at 1d,0 Nothing there
Probing /pci at 1f,4000 at Device 1 pci108e,1000 network
Probing /pci at 1f,4000 at Device 3 scsi disk tape scsi disk tape
Probing /pci at 1f,4000 at Device 2 Nothing there
Probing /pci at 1f,4000 at Device 4 Nothing there
Probing /pci at 1f,4000 at Device 5 Nothing there
Probing /pci at 1f,2000 at Device 1 Nothing there
screen not found.
Can't open input device.
Keyboard not present. Using ttya for input and output.
SC Control: EWP:0 IAP:0 FATAL:0 WAKEUP:0 BXIR:0 BPOR:0 SXIR:0 SPOR:1 POR:0
Probing Memory Bank #0 1 1 1 1 : 4 Gigabytes
Probing Floppy: No drives detected
Probing EBUS Nothing there
Probing UPA Slot at 1e,0 Nothing there
Probing UPA Slot at 1d,0 Nothing there
Probing /pci at 1f,4000 at Device 1 pci108e,1000 network
Probing /pci at 1f,4000 at Device 3 scsi disk tape scsi disk tape
Probing /pci at 1f,4000 at Device 2 Nothing there
Probing /pci at 1f,4000 at Device 4 Nothing there
Probing /pci at 1f,4000 at Device 5 Nothing there
Probing /pci at 1f,2000 at Device 1 Nothing there
Sun Enterprise 420R (4 X UltraSPARC-II 450MHz), No Keyboard
OpenBoot 3.23, 4096 MB memory installed, Serial #15251333.
Ethernet address 8:0:20:e8:b7:85, Host ID: 80e8b785.
Initializing 1 megs of memory at addr fff48000
Initializing 1 megs
of memory at addr fff00000
Initializing 4095 megs of memory at addr
0 4077
4051
4026
3974
3949
3923
3898
3872
3846
3821
3795
3770
3744
3718
3693
3667
3642
3616
3590
3565
3539
3514
3488
3462
3437
34
3386
3360
3334
3309
3283
3258
3232
3206
3181
3155
3130
3104
3078
3053
3027
3002
2976
2950
2925
2899
2874
2848
2822
2797
2771
2746
2720
2694
2669
2643
2618
2592
2566
2541
2515
2490
2464
2438
2413
2387
2362
2336
2310
2285
2259
22
2208
2182
2157
2131
2106
2080
2054
2029
2003
1978
1952
1926
1901
1875
1850
1824
1798
1773
1747
1722
1696
1670
1619
1594
1568
1542
1517
1491
1466
1440
1414
1389
1363
1338
1312
1286
1261
1235
1210
1184
1158
1133
1107
1082
1030
1005
979
954
928
902
877
851
826
800
774
749
723
698
672
646
621
595
570
544
518
493
4
442
416
390
365
339
314
288
262
237
211
186
160
134
109
83
58
32
6
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