[rescue] OT: FeeCee rescue

[Peter Corlett]

Joshua D. Boyd <jdboyd at celestrion.celestrion.net> wrote:
[...]
> I'm told that MIPSpro mainly only uses 4 out of the 32 registers a MIPS
> chip has, except for special cases (which would be tight loops that don't
> make function calls mainly). What I'm seeing looking through tons of
> Hitachi SH-3 assembly code (obviously a non-scientific survey) suggests
> that GCC for this chip doesn't use very many registers either. I'm
> beginning to wonder if lots of general purpose registers is quite what its
> cracked up to be.

It may well be helpful for heavily-inlined C++ code. Nonobvious things can
suddenly become local variables. You'd also get to keep a large struct (or
parts thereof) in registers instead of L1 cache.

I think we've already thrashed out gcc's x86-centricity on this list, so
it's not entirely surprising that you'll find it's not sure what to do on a
CPU that's actually got some registers :)

FWIW, GCC 3.2.3 seems to be OK on m68k, but that's got fewer registers
(which are still slightly dedicated to tasks) than MIPS/SPARC/PPC, etc.

-- 
ISIHAC game to complete Christmas cracker jokes:
Humph: Jeremy, what do you get if you eat too many Christmas decorations?
Jeremy: Yule logs.
Humph: The answer is "tinselitis".