[rescue] J90 on epay

[Joshua D. Boyd]

On Sat, Mar 01, 2003 at 03:48:20PM -0500, Dave McGuire wrote:

>    In mine you mean?  My J90 has three IOSs...two in one VME64 chassis 
> and one in a second.  subsystems.  Each IOS has an IOBB interface going 
> into the mainframe.  See below for more details on this.

I think you might have shown me the innards of Doug's, not yours.
 
>    As far as I'm aware, the IOS SS5s set up DMA transactions between the 
> peripheral controllers and the IOBB board.  What happens then is 
> unclear...I'm not sure if the IOBB board buffers the data then DMAs it 
> into the J90's memory during a second transaction, or if it's more of a 
> "passthrough" interface.

OK.  Perhaps it is capable of operating both ways.  Specially designed
periphs do a passthrough, off the shelf periphs require two
transactions.  Or maybe it does passthrough in a manner that allows the
use of off the shelf boards.

I've heard reports of off the shelf cards being used.  In particular, I
heard one report of someone hooking a serial keyboard and mouse up, and
adding a frame buffer to use the machine interactively.  Well, this
might have been a J90 specifically.  I just remeber it being some YMP
compatible machine.
 
>    For booting, the IOS SS5 (the "master" IOS if there's more than one) 
> keeps the J90 processor halted, squirts a kernel into their memory 
> along with a configuration file which contains details device 
> configuration and such, then starts the processor at the entry point of 
> the kernel.  It's a fascinating process.  It took James Sharp and I 
> days of work to reverse-engineer how the boot process works.

How much of the machine have you managed to figure out?  Enough of the
machine code to be able to make a start of coding ones own OS?
 
>    Each IOS VME64 chassis' backplane is broken into four segments and 
> can hold four separate IOS board sets...each with its own SS5, IOBB, 
> and disk/network interfaces.  An IOBB interface connects via a big fat 
> cable to a mezzanine card mounted in one of the J90 CPU modules.  Each 
> CPU module has four mezzanine slots which can hold either an IOBB 
> interface, a HIPPI source board, or a HIPPI destination board.  With 
> four mezzanine slots on each CPU module, and a maximum of four CPU 
> modules in a J916, that means up to sixteen IOSs.  Most have one or two 
> at most.  A minimally-configured J90 consists of two cabinets, and a 
> big one can be up to five.

I had no idea that HIPPI would be installed as something other than
VME64.  Is this for latency reasons, or is VME64 not as fast as I would
have expected?  For some reason, I expected that VME64 would be faster
than PCI/X.
 
>    The EL family boots in the same way, except the IOS (which is a VME 
> 68020 CPU board) boots from a locally-attached SCSI disk instead of 
> over the ethernet from the OWS.  It uses a regular ASCII console 
> terminal connected to the "master" (if there's more than one) IOS's 68K 
> CPU board.

68020s seem to be used a lot as FEPs.  They are cool little chips.  I
wish I had more time hack on those older 680x0 machines.