[rescue] quad 486

[Tim H.]

On Fri, 21 Feb 2003 10:21:47 -0800 (PST)
Brian <bri at sonicboom.org> wrote:

> Because then there is battling over cache access, and at a lower rate
> than the processor.  Suppose the 2 procs need something different from
> the cache, or suppose sometjing was there but now isn't because it was
> displaced by a request of the other processor.  I knew someone with a
> dual proc p166, and the way he described it to me, was that a lot of
> apps actually performed worse.
> 
> 
> 	Brian
> 
> The path to a desireable destination
> is often more difficult than the path to stay where you are.
> 
> On Fri, 21 Feb 2003, Joshua D. Boyd wrote:
> 
> > On Fri, Feb 21, 2003 at 09:39:04AM -0800, Brian wrote:
> > > I would be hesitant to use smp on a box with procs whose L2 cache
> > > is not on chip..
> >
> > Why do you say that?
> > _______________________________________________
> > rescue list - http://www.sunhelp.org/mailman/listinfo/rescue
> _______________________________________________
> rescue list - http://www.sunhelp.org/mailman/listinfo/rescue
> 
Part of the beauty of the 486 was that before the DX[24] they actually
ran at FSB speed, in fact, if you could find cards that would run at the
unsupported speed, the 486DX50 was a pretty quick chip, significantly
quicker for many apps than the DX266 or even DX4100 (with 33MHz busses).
 Besides, not having L2 on chip in no way prevents you from having
separate L2 for every processor.  Cache coherency is one of the
fundamental problems with SMP, and just because some methods don't work
well doesn't mean that all methods don't work well.