[rescue] Re: Re: OH YEA??? [was: Re: Ultra?]

[Chris Hedemark]

On Sun, 2002-08-04 at 16:20, Dave McGuire wrote:

>   40mhz vs. 270MHz is an important point, but let's also keep in mind
> that this is an apples/oranges comparison.  With 1MB of cache, that
> 40Mhz can actually do some serious work...while the 256K cache on the
> U5's CPU is a joke.

Relevant excerpts from OpenBSD dmesg on U5 and SS10.  Just the facts,
ma'am.

[U5]
mainbus0 (root): SUNW,Ultra-5_10
cpu0 at mainbus0: SUNW,UltraSPARC-IIi @ 333 MHz, version 0 FPU
cpu0: physical 32K instruction (32 b/l), 16K data (32 b/l), 2048K
external (64 b/l)

-vs-

[SS10]
mainbus0 (root): SUNW,SPARCstation-10
cpu0 at mainbus0: TMS390Z50 v0 or TMS390Z55 @ 50 MHz, on-chip FPU
cpu0: physical 20K instruction (64 b/l), 16K data (32 b/l), 1024K
external (32 b/l) cache enabled

Just wanna put that cache myth to rest.

-- 
***********************************************************
| Rev. Chris Hedemark, DD
| Hillsborough, NC
| http://yonderway.com
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| "Opportunity is missed by most people because it is 
| dressed in overalls and looks like work."
|                      Thomas A. Edison
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