Patch Name: PHNE_18767 Patch Description: s700_800 10.20 2.40 ACC HDLC/LAP-B FW Patch Creation Date: 99/06/20 Post Date: 99/11/15 Hardware Platforms - OS Releases: s700: 10.20 s800: 10.20 Products: Z7408AA APZ Filesets: ACC-HDLC.ACC-HDLC-FW Automatic Reboot?: No Status: General Release Critical: No Path Name: /hp-ux_patches/s700_800/10.X/PHNE_18767 Symptoms: PHNE_18767: SR None / DTS TPO0h01780 The LAPB and LAPD protocols were not behaving correctly in relation to retransmission of the REJect frame. Only one REJect frame would be transmitted, despite never receiving an in-sequence I-frame which clears the reject condition. The standards state that that a REJect frame should be retransmitted every T1 interval until the condition clears. SR None / DTS TPO0h01967 Some ports on some 8-port cards fail to come up in X.21 mode. SR None / DTS TPO0h02172 LAPB/LAPD: Extended Information and Supervisory frames that are received and are too short (missing part of control field) are simply being ignored. Receipt of these frames should result in the following action: LAPB - sends FRMR (w and x set) LAPD - sends SABME SR None / DTS TPO0h02173 On LAPB/LAPD connection establishment, groups of DM frames are sent between groups of SABM/SABME frames - which is incorrect. DM frames should not be sent during this connection establishment state. SR None / DTS TPO0h02175 LAPB/LAPD terminals are not handling the "busy condition" properly. If one side of a link is inactive (sent RNR - Receiver Not Ready), the other side should poll every T1 until the remote end activates. SR None / DTS TPO0h02256 The LAPB Z180 firmware blocks messages from being sent after a link reset under special circumstances: A received frame with a bad N(R) will result in a FRMR being sent. On receiving this, the remote end will send a SABM, our end send a UA and the link is re-established. This is fine. But once this process is through, the firmware refuses to send I-frames until it receives a frame. This is a defect. SR None / DTS TPO0h02414 A customer would like to be able to congigure the frame protocol buffer transmit timer in the same way timers are configured in HDLC-LAPB. A problem exists at baud rates of 1200 and below. A full buffer of data (238 bytes) will be cut short when the 1 second transmit timeout expires. SR None / DTS TPO0h02429 The ACC loopback test (invoked by the LB command in zmntr) was occasionally failing with non-defective 8-port cards. The problem occurred on average about once every 50 zmntr LB commands. SR None / DTS TPO0h02504 With the baud rate incorrectly configured as 64,000 while the actual line speed is 9600, transmitted frames can be cut short and joined together. SR None / DTS TPO0h02773 Some ports on some cards do not work properly in X.21 mode on the 8-port NIO and EISA cards. Some of these failures occur just after a card reset, and recover after some 10 - 30 seconds. Other ports fail all the time. The failure appears to be the port detecting the CTS and/or DCD signals missing. PHNE_15352: SR None / DTS TPO0h01936 4-ch card: A DMA timeout can occur when disabling LAPD devices. SR None / DTS TPO0h02042 4-ch card: LAPB/LAPD loses timers in the timer download control request. SR None / DTS TPO0h01946 4-ch card: LAPB/LAPD can get frames out of sequence after receiving a REJ. SR 4701391862 / DTS TPO0h01966 No current method to determine hardware revision PHNE_14053: SR None / DTS TPO0h01833 8-channel NIO card crashes, with the use of the frame protocol and hdlcabm protocol together on the same port. SR None / DTS TPO0h01640 2 channel ACC card transmits a bad frame at the beginning of link setup. SR None / DTS TPO0h01641 When an unrecognised unnumbered frame is received at level2, the cause code information in the generated frame reject is incorrect. SR None / DTS TPO0h01755 hdlcabm sentr REJ on I-frame with duplicate N(s) Defect Description: PHNE_18767: SR None / DTS TPO0h01780 The HDLCABM state machine was not designed to handle REJect frame retransmission. Extensive changes have been made to the HDLCABM state machine to handle REJect frame retransmission. DTS TPO0h01967 Change to ensure that X.21 is disabled for the Z7200A Rev.A card only. Change particularly focused at the Z7400A EISA cards to ensure that Rev.A cards are not disabled from X.21 configuration. This corrects the X.21 configuration problem with all cards. SR None / DTS TPO0h02172 HDLC firmware was ignoring this condition. The HDLC firmware has been corrected. SR None / DTS TPO0h02173 Bad state change on N2/N200 timer expiration. The finite state machine (FSM) has been corrected. SR None / DTS TPO0h02175 Incorrect behaviour coded into the HDLCABM state machine. The state machine has been corrected. SR None / DTS TPO0h02256 The transmit window full flag in the firmware was not being cleared on the link reset. The firmware did not send further messages because it thought the window was full. Code to reset this transmit window full flag have been added in the appropriate points. SR None / DTS TPO0h02414 The transmit timeout is fixed at 1 second which is not enough to allow the complete transmission of a full buffer (238 bytes) at 1200 baud or less. The frame module now sets the timeout according to the configured baud rate on the port. Baud rate Tx timeout (x100ms) 300 136 600 69 1200 35 2400 18 4800 10 9600 6 >9600 4 These timeouts allow approximately double the necessary time for the maximum of 252 bytes to be transmitted. 252 bytes is the maximum number of bytes to be transmitted because that is the maximum which can be held in one ACC buffer. SR None / DTS TPO0h02429 A problem with the 8-port's ISCC chips caused a transmit underrun to be incorrectly generated during the start of a frame tranmission - resulting in the first few bytes of that frame being corrupt. Note: The test is transmitting in single character mode. On initialisation of the ISCC, the firmware was issuing a "Reset Tx Underrun/EOM Latch" command. This was found to cause the occasional transmit underrun external/status interrupt. This reset command was taken out of the initialisation sequence in the testprot firmware. SR None / DTS TPO0h02504 This is due to an enhancement that was made for defect TPO0h02414. The transmit timeout used at level-1 was shortened for baud rates as high as 64000. Because incorrect baud rate configurations can lead to this problem, part of the changes made for TPO0h02414 have now been backed out. The minimum timeout used is now 1 second which will allow for typical incorrect configurations. SR None / DTS TPO0h02773 The Sipex chips (line drivers) when placed in RS422 mode (balanced signaling mode used for X.21) leave some unused TTL output pins in an unknown state. These pins are used for the CTS signal when the Sipex chip is in RS232 mode. The firmware was reading the state of the CTS signal - and the ISCC chips were configured to react to this signal. This problem was not detected before because the usual state of these Sipex pins signal that CTS is up. On some Sipex chips, this signal is down, or is down and then comes up after a short period of time after being put into RS422 mode. The firmware has been changed to ignore the CTS signal when in X.21 mode. Also the ISCC chips are configured to also ignore changes in the CTS and DCD signals. The firmware code still checks the DCD signal - which matches the X.21 Indicate signal, so the firmware still can detect a cable disconnect. Note: There is no problem in ignoring the (internal) CTS signal - as it does not map to any signal in X.21. PHNE_15352: SR None / DTS TPO0h01936: 4-ch card: When disabling LAPD devices which are under high message load the E1/T1 ACC card can "DMA timeout" due to internal linkages between remaining devices on the same subchannel being corrupted. SR None / DTS TPO0h02042: 4-ch card: When timers are downloaded to the LAPB/LAPD protocol in the CW_TIMERS control write request, a system timer entry is wasted. Eventually the ACC card can run out of timers. SR None / DTS TPO0h01946: 4-ch card: When the HDLCABM or X25 protocol receives a REJ frame while it is in the process of retransmitting frames, it can get transmitted frames out of sequence. SR 4701391862 / DTS TPO0h01966 Enhancement to detect hardware revisions of ACC cards. A standard interface has been defined to identify hardware revisions of all ACC cards. The 'mx' command of zmntr has been enhanced to include the display of the hardware revision. PHNE_14053: SR None / DTS TPO0h01833 Firmware failures with FRAME and HDLCABM concurrently in use. SR None / DTS TPO0h01640 2ch card transmits bad frame on link startup SR None / DTS TPO0h01641 frame reject cause information is bad on unknown frame type SR None / DTS TPO0h01755 hdlcabm sends REJ on I-frame with duplicate N(s) SR: 4701380642 4701391862 Patch Files: /opt/acc/z7200a/hdlc.zmap /opt/acc/z7350a/hdlc.zmap /opt/acc/z7400a/hdlc.zmap /opt/acc/z7200a/hdlc.zabs /opt/acc/z7350a/hdlc.zabs /opt/acc/z7400a/hdlc.zabs /opt/acc/protocol/hdlcabm.zrel what(1) Output: /opt/acc/z7200a/hdlc.zmap: ZCOM System Firmware (ROM) Rev 04.B 921106.1200 ACC Rel B.02.40 for B.10.20 PHNE_14053 z7200_snp.z8 0 ZCOM System Software (WMUX1) ACC Rel B.02.40 for B.10.20 PHNE_14053 wmux1.z80 ZCOM System Software (WMUX3) ACC Rel B.02.40 for B.10.20 PHNE_14053 wmux3.z80 CPU clock 16MHz ZCOM System Software (WMUX4) ACC Rel B.02.40 for B.10.20 PHNE_14053 wmux4.z80 ZCOM LEVEL1 Protocol ACC Rel B.02.40 for B.10.20 PHNE_14053 level1.z80 ZCOM HDLC ABM Protocol ACC Rel B.02.40 for B.10.20 PHNE_14053 abm.cpp ZCOM HDLC ABM State Tables Rev:1.12 971128.1444 ACC Rel B.02.40 for B.10.20 PHNE_14053 abmfsmtab.zi nc ZCOM Monitor Module ACC Rel B.02.40 for B.10.20 PHNE_14053 monitor.z80 ZCOM Port Diagnostic Module ACC Rel B.02.40 for B.10.20 PHNE_14053 testprot.z80 ZCOM Protocol Module Entry Point Table ACC Rel B.02.40 for B.10.20 PHNE_14053 pmenttab.z80 ZCOM System Entry Point Table ACC Rel B.02.40 for B.10.20 PHNE_14053 umuxent.z80 /opt/acc/z7350a/hdlc.zmap: ZCOM System Firmware (ROM) Rev 01.T5 ACC Rel B.02.40 for B.10.20 PHNE_14053 z7350_rom.z8 0 ZCOM Z7350A System Software ACC Rel B.02.40 for B.10.20 PHNE_14053 z7350_fw.z80 CPU clock 32MHz ZCOM LEVEL1 Protocol ACC Rel B.02.40 for B.10.20 PHNE_14053 level1.z80 ZCOM HDLC ABM Protocol ACC Rel B.02.40 for B.10.20 PHNE_14053 abm.cpp ZCOM HDLC ABM State Tables Rev:1.12 971128.1444 ACC Rel B.02.40 for B.10.20 PHNE_14053 abmfsmtab.zi nc ZCOM Monitor Module ACC Rel B.02.40 for B.10.20 PHNE_14053 monitor.z80 ZCOM Port Diagnostic Module ACC Rel B.02.40 for B.10.20 PHNE_14053 testprot_ius c.z80 ZCOM Protocol Module Entry Point Table ACC Rel B.02.40 for B.10.20 PHNE_14053 pmenttab.z80 /opt/acc/z7400a/hdlc.zmap: ZCOM System Firmware (ROM) Rev 01.B5 ACC Rel B.02.40 for B.10.20 PHNE_14053 z7400_rom.z8 0 ZCOM Z7400A System Software ACC Rel B.02.40 for B.10.20 PHNE_14053 z7400_fw.z80 ZCOM LEVEL1 Protocol ACC Rel B.02.40 for B.10.20 PHNE_14053 level1.z80 ZCOM HDLC ABM Protocol ACC Rel B.02.40 for B.10.20 PHNE_14053 abm.cpp ZCOM HDLC ABM State Tables Rev:1.12 971128.1444 ACC Rel B.02.40 for B.10.20 PHNE_14053 abmfsmtab.zi nc ZCOM Monitor Module ACC Rel B.02.40 for B.10.20 PHNE_14053 monitor.z80 ZCOM Port Diagnostic Module ACC Rel B.02.40 for B.10.20 PHNE_14053 testprot.z80 ZCOM Protocol Module Entry Point Table ACC Rel B.02.40 for B.10.20 PHNE_14053 pmenttab.z80 /opt/acc/z7200a/hdlc.zabs: ZCOM System Firmware (ROM) Rev 04.B 921106.1200 ACC Rel B.02.40-B.2.40.02 for B.10.20 PHNE_18767 z7 200_s ZCOM System Software (WMUX1) ACC Rel B.02.40-B.2.40.02 for B.10.20 PHNE_18767 wm ux1.z ZCOM System Software (WMUX3) ACC Rel B.02.40-B.2.40.02 for B.10.20 PHNE_18767 wm ux3.z CPU clock 16MHz ZCOM System Software (WMUX4) ACC Rel B.02.40-B.2.40.02 for B.10.20 PHNE_18767 wm ux4.z ZCOM LEVEL1 Protocol ACC Rel B.02.40-B.2.40.02 for B.10.20 PHNE_18767 le vel1. ZCOM HDLC ABM Protocol ACC Rel B.02.40-B.2.40.02 for B.10.20 PHNE_18767 ab m.cpp Patch version: PHNE_18767 ZCOM HDLC ABM State Tables Rev:1.12 981123.1126 ACC Rel B.02.40-B.2.40.02 for B.10.20 PHNE_18767 ab mfsmt ZCOM Monitor Module ACC Rel B.02.40-B.2.40.02 for B.10.20 PHNE_18767 mo nitor ZCOM Port Diagnostic Module ACC Rel B.02.40-B.2.40.02 for B.10.20 PHNE_18767 te stpro ZCOM Protocol Module Entry Point Table ACC Rel B.02.40-B.2.40.02 for B.10.20 PHNE_18767 pm entta ZCOM System Entry Point Table ACC Rel B.02.40-B.2.40.02 for B.10.20 PHNE_18767 um uxent /opt/acc/z7350a/hdlc.zabs: ZCOM System Firmware (ROM) Rev 01.T5 ACC Rel B.02.40-B.2.40.02 for B.10.20 PHNE_18767 z7 350_r ZCOM Z7350A System Software ACC Rel B.02.40-B.2.40.02 for B.10.20 PHNE_18767 z7 350_f CPU clock 32MHz ZCOM LEVEL1 Protocol ACC Rel B.02.40-B.2.40.02 for B.10.20 PHNE_18767 le vel1. ZCOM HDLC ABM Protocol ACC Rel B.02.40-B.2.40.02 for B.10.20 PHNE_18767 ab m.cpp Patch version: PHNE_18767 ZCOM HDLC ABM State Tables Rev:1.12 981123.1126 ACC Rel B.02.40-B.2.40.02 for B.10.20 PHNE_18767 ab mfsmt ZCOM Monitor Module ACC Rel B.02.40-B.2.40.02 for B.10.20 PHNE_18767 mo nitor ZCOM Port Diagnostic Module ACC Rel B.02.40-B.2.40.02 for B.10.20 PHNE_18767 te stpro ZCOM Protocol Module Entry Point Table ACC Rel B.02.40-B.2.40.02 for B.10.20 PHNE_18767 pm entta /opt/acc/z7400a/hdlc.zabs: ZCOM System Firmware (ROM) Rev 01.B5 ACC Rel B.02.40-B.2.40.02 for B.10.20 PHNE_18767 z7 400_r ZCOM Z7400A System Software ACC Rel B.02.40-B.2.40.02 for B.10.20 PHNE_18767 z7 400_f ZCOM LEVEL1 Protocol ACC Rel B.02.40-B.2.40.02 for B.10.20 PHNE_18767 le vel1. ZCOM HDLC ABM Protocol ACC Rel B.02.40-B.2.40.02 for B.10.20 PHNE_18767 ab m.cpp Patch version: PHNE_18767 ZCOM HDLC ABM State Tables Rev:1.12 981123.1126 ACC Rel B.02.40-B.2.40.02 for B.10.20 PHNE_18767 ab mfsmt ZCOM Monitor Module ACC Rel B.02.40-B.2.40.02 for B.10.20 PHNE_18767 mo nitor ZCOM Port Diagnostic Module ACC Rel B.02.40-B.2.40.02 for B.10.20 PHNE_18767 te stpro ZCOM Protocol Module Entry Point Table ACC Rel B.02.40-B.2.40.02 for B.10.20 PHNE_18767 pm entta /opt/acc/protocol/hdlcabm.zrel: ZCOM HDLC ABM Protocol ACC Rel B.02.40-B.2.40.02 for B.10.20 PHNE_18767 ab m.cpp Patch version: PHNE_18767 ZCOM HDLC ABM State Tables Rev:1.12 981123.1126 ACC Rel B.02.40-B.2.40.02 for B.10.20 PHNE_18767 ab mfsmt cksum(1) Output: 852565348 19488 /opt/acc/z7200a/hdlc.zmap 3579587064 18325 /opt/acc/z7350a/hdlc.zmap 3878028501 18152 /opt/acc/z7400a/hdlc.zmap 3794672336 25674 /opt/acc/z7200a/hdlc.zabs 1284273392 24848 /opt/acc/z7350a/hdlc.zabs 4040355073 25732 /opt/acc/z7400a/hdlc.zabs 2145155890 30070 /opt/acc/protocol/hdlcabm.zrel Patch Conflicts: None Patch Dependencies: s700: 10.20: PHNE_18716 s800: 10.20: PHNE_18716 Hardware Dependencies: None Other Dependencies: None Supersedes: PHNE_14053 PHNE_15352 Equivalent Patches: None Patch Package Size: 230 KBytes Installation Instructions: Please review all instructions and the Hewlett-Packard SupportLine User Guide or your Hewlett-Packard support terms and conditions for precautions, scope of license, restrictions, and, limitation of liability and warranties, before installing this patch. ------------------------------------------------------------ 1. Back up your system before installing a patch. 2. Login as root. 3. Copy the patch to the /tmp directory. 4. Move to the /tmp directory and unshar the patch: cd /tmp sh PHNE_18767 5a. For a standalone system, run swinstall to install the patch: swinstall -x autoreboot=true -x match_target=true \ -s /tmp/PHNE_18767.depot By default swinstall will archive the original software in /var/adm/sw/patch/PHNE_18767. If you do not wish to retain a copy of the original software, you can create an empty file named /var/adm/sw/patch/PATCH_NOSAVE. WARNING: If this file exists when a patch is installed, the patch cannot be deinstalled. Please be careful when using this feature. It is recommended that you move the PHNE_18767.text file to /var/adm/sw/patch for future reference. To put this patch on a magnetic tape and install from the tape drive, use the command: dd if=/tmp/PHNE_18767.depot of=/dev/rmt/0m bs=2k Special Installation Instructions: SUBSYSTEM_SHUT After installing this patch, the ACC subsystem must then be stopped and restarted using zmasterd in order to download the new firmware.