The contents of the following registers can be viewed. The complete register contents are shown in raw (32-bit hexadecimal) form; by clicking on the plus (+) sign to the left of the register name, key fields in the register are identified and their values are interpreted.
NOTE: For all multi-field registers (all but the SPA Revision register), the fields that are broken out separately for viewing are underscored in the tables that follow.
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0x03 | SHIP 1.5C | ServerNet PCI Adapter Version 2 | Earliest version of SPA that can be used with NonStop Clusters operating environment, release E00 (or later). SHIP is the internal name for the SPA. |
0x05 | SHIP 1.5E | ServerNet PCI Adapter Version 3 | Second version of SPA that can be used with NonStop Clusters operating environment, release E00 (or later). |
28-31 | ASIC Version | Identifies the version of the SAIL ASIC |
12-27 | ASIC ID | SAIL ASIC ID = 0x001C |
1-11 | ASIC Manufacturer | Manufacturer = Tandem = 0x53 |
0 | None | Not used; always 1 |
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31 | Parity | Odd parity bit |
20-30 | None | Not used |
0-19 | ServerNet SAN (TNet) Node ID | Node 1 = F0040
Node 2 = F0080 Node 3 = F00C0 Node 4 = F0100 Node 5 = F0140 Node 6 = F0180 |
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31 | Parity | Odd parity bit. |
18-30 | None | Not used. |
17 | LL_SC_En | Link layer self check enable. LLSC includes RunOn Packet Timeout, BackPressure Timeout, and Source ID check only. When this bit is set to 1, these sources of self checking are enabled. When it is set to 0, self checking is disabled. |
16 | LL_SC_EN_N | Link layer self-check enable (inverted). This bit must be set to the opposite value of LL_SC_En. If LL_SC_En and LL_SC_En_N are set to the same value (00 or 11), the SAIL ASIC self checks and both ServerNet SAN ports on the SPA transmit this-link-bad (TLB) command symbols. |
14,15 | Reserved | Both set to 0. |
13 | EndianMode | When this bit is set to 0, the SAIL ASIC operates in big-endian mode. When it is set to 1, the SAIL ASIC operates in little-endian mode. |
12 | Inv RxClk | Inverted receive clock. When this bit is set to 1, the receiver synchronous FIFO logic is operating with an inverted RxClk. |
9-11 | None | Not used. |
8 | PortSwap | This bit is used to change the physical port assignment for ServerNet SAN ports X and Y. If this bit is set to 1, then the external X and Y port operations are swapped (that is, X port operations will occur on the Y port pins and vice versa). |
4,5 | None | Not used. |
2,3,6,7 | Reserved | All set to 0. |
0,1 | Reserved | Both set to 1. |
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15-31 | None | Not used. |
14 | Timebase Restart | When set to 1, the time-based counters are restarted. The first ServerNet SAN link layer keepalive symbol (READY, BUSY, or SKIP) is transmitted eight clocks after this bit is set, the second symbol is transmitted an additional 512 clocks later. |
13 | None | Not used. |
12 | Reserved | Set to 0. |
10,11 | X Port Receive Rst/Enb | Bit 11 is the port X receiver reset control (set to 1 to reset the port X receiver). Bit 10 is the port X receiver enable control (set to 1 to enable operation of the port X receiver). |
8,9 | X Port Transmit Rst/Enb | Bit 9 is the port X transmitter reset control (set to 1 to reset the port X transmitter). Bit 8 is the port X transmitter enable control (set to 1 to enable operation of the port X transmitter). |
5-7 | None | Not used. |
4 | Reserved | Set to 0. |
2,3 | Y Port Receive Rst/Enb | Bit 3 is the port Y receiver reset control (set to 1 to reset the port Y receiver). Bit 2 is the port Y receiver enable control (set to 1 to enable operation of the port Y receiver). |
0,1 | Y Port Transmit Rst/Enb | Bit 1 is the port Y transmitter reset control (set to 1 to reset the port Y transmitter). Bit 0 is the port Y transmitter enable control (set to 1 to enable operation of the port Y transmitter). |
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31 | Perf_int | Performance interrupt events mask bit. |
30,
24-29 |
NQ NMI,
NQ IP2-NQ IP7 |
Non-queued interrupts mask bits. |
23 | ExcQueErr | Exception queue error interrupt mask bit. |
22 | WrReqOverflow | Write request overflow interrupt mask bit. |
21 | Access_Err | Unmasked access errors from the IIF_Status register interrupt mask bit. |
20 | IIF_Self_Check | Unmasked IIF_Status conditions interrupt mask bit. If mask bit is set, SAIL ASIC is still in self check and self-check recovery is required. |
19 | RdReqOverflow | Read request overflow interrupt mask bit. |
18 | Queue Full | Queue full conditions interrupt mask bit. |
17 | BTE1Done | BTE channel 1 completions interrupt mask bit. |
16 | BTE0Done | BTE channel 0 completions interrupt mask bit. |
15 | TNet_Self_Check | Unmasked TNet_Self_Check conditions interrupt mask bit. If mask bit is set, SAIL ASIC is still in self check and self-check recovery is required. |
14,
8-13 |
Q NMI,
Q IP2-Q IP7 |
Queued interrupts mask bits. |
7 | None | Not used. |
6 | Reserved | Set to 0. |
5 | ATTN Rcvd X | ATTN commands received on port X interrupt mask bit. |
4 | Link Exc X | Link exceptions detected on port X interrupt mask bit. |
3 | None | Not used. |
2 | Reserved | Set to 0. |
1 | ATTN Rcvd Y | ATTN commands received on port Y interrupt mask bit. |
0 | Link Exc Y | Link exceptions detected on port Y interrupt mask bit. |