[SunHELP] Sparc 20 keeps on Panicing
Sevan / Venture37
venture37 at hotmail.com
Thu Feb 19 22:14:33 CST 2004
Hi
I have a Quad 100 Ross Sparc 20 which keeps on panicing, I've swapped the HD
out twice & lowlevel formatted the discs on a pc using the adaptec scsi
bios lowlevel format util. I've also ran the diag boot & checked the output
via the serial console,everything seems to be right, yet I cant boot off
either solaris 8 or 9 cd's, I found a ross white paper on planet mirror
which reckons it mean a dud cpu but I want to be a 110% sure
heres the output from the diag boot & the panic data thats shown on the
screen b4 the system syncs & reboots:
SMCC SPARCstation 10/20 UP/MP POST version VRV3.45 (09/11/95)
CPU_#0 HyperSPARC ROSS RT620/RT625 0x00040000 Bytes ECache
CPU_#1 HyperSPARC ROSS RT620/RT625 0x00040000 Bytes ECache
CPU_#2 HyperSPARC ROSS RT620/RT625 0x00040000 Bytes ECache
CPU_#3 HyperSPARC ROSS RT620/RT625 0x00040000 Bytes ECache
<<< CPU_00000000 on MBus Slot_00000000 >>> IS RUNNING (MID = 00000008)
$$$$$ WARNING : No Keyboard Detected! $$$$$
HyperSparc Context Pointer Reg Test
HyperSparc Context Reg Test
HyperSparc Root Pointer Reg Test
HyperSparc Instr Pointer Reg Test
HyperSparc Data Pointer Reg Test
HyperSparc Index Tag Reg Test
HyperSparc TLB Replace Reg Test
HyperSparc TLB RAM bit pattern Test
HyperSparc TLB/CAM NTA pattern Test
HyperSparc MMU tlbmiss_test
HyperSparc MMU_tlbhit_test
HyperSparc MMU Flush Tests
HyperSparc ECache RAM W/R Test Ec_size=0x00040000
HyperSparc ECache Tag NTA Test
HyperSparc ICache RAM Test Ic_size=0x00002000
HyperSparc ICache Tag NTA Test
HyperSparc Write buffer/write-thru mode
HyperSparc Write buffer/copy-back mode
HyperSparc Block copy test/mmu_off
HyperSparc Block fill test/mmu_off
HyperSparc Block Copy Test/MMU_ON
HyperSparc Block Fill Test/MMU_ON
EMC/SMC Control Regs Tests
ECC Multiple UE Test
ECC Multiple CE Test
ECC Multiple CE, UE Test
FPU Register File Test
FPU Misaligned Reg Pair Test
FPU Single-precision Tests
FPU Double-precision Tests
FPU SP Invalid CEXC Test
FPU SP Overflow CEXC Test
FPU SP Divide-by-0 CEXC Test
FPU SP Inexact CEXC Test
FPU SP Trap Priority > Test
FPU SP Trap Priority < Test
FPU SP UE Trap Priority Test
FPU DP Invalid CEXC Test
FPU DP Overflow CEXC Test
FPU DP Divide-by-0 CEXC Test
FPU DP Inexact CEXC Test
FPU DP Trap Priority > Test
FPU DP Trap Priority < Test
FPU DP UE Trap Priority Test
FPU DP CE Trap Priority Test
Memory Address Pattern Test
System Interrupt Regs Tests
PROC0 Interrupt Regs Tests
Soft Interrupts OFF Test
Soft Interrupts ON Test
PROC0 User Timer Test
PROC0 Counter/Timer Test
System Counter Test
MSI/MSBI Control Reg Tests
IOMMU CAM NTA Pattern Test
IOMMU TLB NTA Pattern Test
IOMMU CAM TLB Comparator Test
IOMMU TLB Flush Tests
DMA2/MACIO ID Register Test
DMA2/MACIO E_CSR Reg. Test
LANCE Address Port Tests
LANCE Data Port Tests
DMA2/MACIO D_CSR Reg. Test
DMA2/MACIO D_ADDR Reg. Test
DMA2/MACIO D_BCNT Reg. Test
DMA2/MACIO D_NADDR Reg. Test
ESP Registers Tests
DMA2/MACIO P_CSR Reg. Test
DMA2/MACIO P_ADDR Reg. Test
DMA2/MACIO P_BCNT Reg. Test
PPORT Registers Tests
DMA2/MACIO PPORT IO Lpbck Tst
DMA2/MACIO PPORT XFR Lbck Tst
TOD Registers Test
<<< CPU_00000001 on MBus Slot_00000000 >>> IS RUNNING (MID = 00000009)
HyperSparc Context Pointer Reg Test
HyperSparc Context Reg Test
HyperSparc Root Pointer Reg Test
HyperSparc Instr Pointer Reg Test
HyperSparc Data Pointer Reg Test
HyperSparc Index Tag Reg Test
HyperSparc TLB Replace Reg Test
HyperSparc TLB RAM bit pattern Test
HyperSparc TLB/CAM NTA pattern Test
HyperSparc MMU tlbmiss_test
HyperSparc MMU_tlbhit_test
HyperSparc MMU Flush Tests
HyperSparc ECache RAM W/R Test Ec_size=0x00040000
HyperSparc ECache Tag NTA Test
HyperSparc ICache RAM Test Ic_size=0x00002000
HyperSparc ICache Tag NTA Test
HyperSparc Write buffer/write-thru mode
HyperSparc Write buffer/copy-back mode
HyperSparc Block copy test/mmu_off
HyperSparc Block fill test/mmu_off
HyperSparc Block Copy Test/MMU_ON
HyperSparc Block Fill Test/MMU_ON
EMC/SMC Control Regs Tests
ECC Multiple UE Test
ECC Multiple CE Test
ECC Multiple CE, UE Test
FPU Register File Test
FPU Misaligned Reg Pair Test
FPU Single-precision Tests
FPU Double-precision Tests
FPU SP Invalid CEXC Test
FPU SP Overflow CEXC Test
FPU SP Divide-by-0 CEXC Test
FPU SP Inexact CEXC Test
FPU SP Trap Priority > Test
FPU SP Trap Priority < Test
FPU SP UE Trap Priority Test
FPU DP Invalid CEXC Test
FPU DP Overflow CEXC Test
FPU DP Divide-by-0 CEXC Test
FPU DP Inexact CEXC Test
FPU DP Trap Priority > Test
FPU DP Trap Priority < Test
FPU DP UE Trap Priority Test
FPU DP CE Trap Priority Test
Memory Address Pattern Test
System Interrupt Regs Tests
PROC1 Interrupt Regs Tests
Soft Interrupts OFF Test
Soft Interrupts ON Test
PROC1 User Timer Test
PROC1 Counter/Timer Test
System Counter Test
MSI/MSBI Control Reg Tests
IOMMU CAM NTA Pattern Test
IOMMU TLB NTA Pattern Test
IOMMU CAM TLB Comparator Test
IOMMU TLB Flush Tests
DMA2/MACIO ID Register Test
DMA2/MACIO E_CSR Reg. Test
LANCE Address Port Tests
LANCE Data Port Tests
DMA2/MACIO D_CSR Reg. Test
DMA2/MACIO D_ADDR Reg. Test
DMA2/MACIO D_BCNT Reg. Test
DMA2/MACIO D_NADDR Reg. Test
ESP Registers Tests
DMA2/MACIO P_CSR Reg. Test
DMA2/MACIO P_ADDR Reg. Test
DMA2/MACIO P_BCNT Reg. Test
PPORT Registers Tests
DMA2/MACIO PPORT IO Lpbck Tst
DMA2/MACIO PPORT XFR Lbck Tst
TOD Registers Test
<<< CPU_00000002 on MBus Slot_00000001 >>> IS RUNNING (MID = 0000000a)
HyperSparc Context Pointer Reg Test
HyperSparc Context Reg Test
HyperSparc Root Pointer Reg Test
HyperSparc Instr Pointer Reg Test
HyperSparc Data Pointer Reg Test
HyperSparc Index Tag Reg Test
HyperSparc TLB Replace Reg Test
HyperSparc TLB RAM bit pattern Test
HyperSparc TLB/CAM NTA pattern Test
HyperSparc MMU tlbmiss_test
HyperSparc MMU_tlbhit_test
HyperSparc MMU Flush Tests
HyperSparc ECache RAM W/R Test Ec_size=0x00040000
HyperSparc ECache Tag NTA Test
HyperSparc ICache RAM Test Ic_size=0x00002000
HyperSparc ICache Tag NTA Test
HyperSparc Write buffer/write-thru mode
HyperSparc Write buffer/copy-back mode
HyperSparc Block copy test/mmu_off
HyperSparc Block fill test/mmu_off
HyperSparc Block Copy Test/MMU_ON
HyperSparc Block Fill Test/MMU_ON
EMC/SMC Control Regs Tests
ECC Multiple UE Test
ECC Multiple CE Test
ECC Multiple CE, UE Test
FPU Register File Test
FPU Misaligned Reg Pair Test
FPU Single-precision Tests
FPU Double-precision Tests
FPU SP Invalid CEXC Test
FPU SP Overflow CEXC Test
FPU SP Divide-by-0 CEXC Test
FPU SP Inexact CEXC Test
FPU SP Trap Priority > Test
FPU SP Trap Priority < Test
FPU SP UE Trap Priority Test
FPU DP Invalid CEXC Test
FPU DP Overflow CEXC Test
FPU DP Divide-by-0 CEXC Test
FPU DP Inexact CEXC Test
FPU DP Trap Priority > Test
FPU DP Trap Priority < Test
FPU DP UE Trap Priority Test
FPU DP CE Trap Priority Test
Memory Address Pattern Test
System Interrupt Regs Tests
PROC2 Interrupt Regs Tests
Soft Interrupts OFF Test
Soft Interrupts ON Test
PROC2 User Timer Test
PROC2 Counter/Timer Test
System Counter Test
MSI/MSBI Control Reg Tests
IOMMU CAM NTA Pattern Test
IOMMU TLB NTA Pattern Test
IOMMU CAM TLB Comparator Test
IOMMU TLB Flush Tests
DMA2/MACIO ID Register Test
DMA2/MACIO E_CSR Reg. Test
LANCE Address Port Tests
LANCE Data Port Tests
DMA2/MACIO D_CSR Reg. Test
DMA2/MACIO D_ADDR Reg. Test
DMA2/MACIO D_BCNT Reg. Test
DMA2/MACIO D_NADDR Reg. Test
ESP Registers Tests
DMA2/MACIO P_CSR Reg. Test
DMA2/MACIO P_ADDR Reg. Test
DMA2/MACIO P_BCNT Reg. Test
PPORT Registers Tests
DMA2/MACIO PPORT IO Lpbck Tst
DMA2/MACIO PPORT XFR Lbck Tst
TOD Registers Test
<<< CPU_00000003 on MBus Slot_00000001 >>> IS RUNNING (MID = 0000000b)
HyperSparc Context Pointer Reg Test
HyperSparc Context Reg Test
HyperSparc Root Pointer Reg Test
HyperSparc Instr Pointer Reg Test
HyperSparc Data Pointer Reg Test
HyperSparc Index Tag Reg Test
HyperSparc TLB Replace Reg Test
HyperSparc TLB RAM bit pattern Test
HyperSparc TLB/CAM NTA pattern Test
HyperSparc MMU tlbmiss_test
HyperSparc MMU_tlbhit_test
HyperSparc MMU Flush Tests
HyperSparc ECache RAM W/R Test Ec_size=0x00040000
HyperSparc ECache Tag NTA Test
HyperSparc ICache RAM Test Ic_size=0x00002000
HyperSparc ICache Tag NTA Test
HyperSparc Write buffer/write-thru mode
HyperSparc Write buffer/copy-back mode
HyperSparc Block copy test/mmu_off
HyperSparc Block fill test/mmu_off
HyperSparc Block Copy Test/MMU_ON
HyperSparc Block Fill Test/MMU_ON
EMC/SMC Control Regs Tests
ECC Multiple UE Test
ECC Multiple CE Test
ECC Multiple CE, UE Test
FPU Register File Test
FPU Misaligned Reg Pair Test
FPU Single-precision Tests
FPU Double-precision Tests
FPU SP Invalid CEXC Test
FPU SP Overflow CEXC Test
FPU SP Divide-by-0 CEXC Test
FPU SP Inexact CEXC Test
FPU SP Trap Priority > Test
FPU SP Trap Priority < Test
FPU SP UE Trap Priority Test
FPU DP Invalid CEXC Test
FPU DP Overflow CEXC Test
FPU DP Divide-by-0 CEXC Test
FPU DP Inexact CEXC Test
FPU DP Trap Priority > Test
FPU DP Trap Priority < Test
FPU DP UE Trap Priority Test
FPU DP CE Trap Priority Test
Memory Address Pattern Test
System Interrupt Regs Tests
PROC3 Interrupt Regs Tests
Soft Interrupts OFF Test
Soft Interrupts ON Test
PROC3 User Timer Test
PROC3 Counter/Timer Test
System Counter Test
MSI/MSBI Control Reg Tests
IOMMU CAM NTA Pattern Test
IOMMU TLB NTA Pattern Test
IOMMU CAM TLB Comparator Test
IOMMU TLB Flush Tests
DMA2/MACIO ID Register Test
DMA2/MACIO E_CSR Reg. Test
LANCE Address Port Tests
LANCE Data Port Tests
DMA2/MACIO D_CSR Reg. Test
DMA2/MACIO D_ADDR Reg. Test
DMA2/MACIO D_BCNT Reg. Test
DMA2/MACIO D_NADDR Reg. Test
ESP Registers Tests
DMA2/MACIO P_CSR Reg. Test
DMA2/MACIO P_ADDR Reg. Test
DMA2/MACIO P_BCNT Reg. Test
PPORT Registers Tests
DMA2/MACIO PPORT IO Lpbck Tst
DMA2/MACIO PPORT XFR Lbck Tst
TOD Registers Test
Available Memory 0x18000000
Allocating SRMMU Context Table
Context Table allocated, Available Memory 0x17ffc000
Setting SRMMU Context Register
Context Table allocated, Available Memory 0x17ffc000
Setting SRMMU Context Table Pointer Register
RAMsize allocated, Available Memory 0x17fec000
Allocating SRMMU Level 1 Table
Level 1 Table allocated, Available Memory 0x17febc00
Mapping RAM @ 0xffef0000
RAM mapped, Available Memory 0x17feba00
Mapping ROM @ 0xffd00000
ROM mapped, Available Memory 0x17feb800
Mapping ROM @ 0x00000000
ROM mapped, Available Memory 0x17feb000
ttya initialized
Cpu #0 Ross,RT625
Cpu #1 Ross,RT625
Cpu #2 Ross,RT625
Cpu #3 Ross,RT625
Probing Memory Bank #0 64 Megabytes of DRAM
Probing Memory Bank #1 Nothing there
Probing Memory Bank #2 Nothing there
Probing Memory Bank #3 Nothing there
Probing Memory Bank #4 Nothing there
Probing Memory Bank #5 64 Megabytes of DRAM
Probing Memory Bank #6 Nothing there
Probing Memory Bank #7 8 Megabytes of VRAM
Probing /obio at 2,0 cgfourteen
Probing /iommu at f,e0000000/sbus at f,e0001000 at f,0 espdma esp sd st ledma le
SUNW
,bpp
Probing /iommu at f,e0000000/sbus at f,e0001000 at e,0 SUNW,DBRIe
Probing /iommu at f,e0000000/sbus at f,e0001000 at 0,0 Nothing there
Probing /iommu at f,e0000000/sbus at f,e0001000 at 1,0 Nothing there
Probing /iommu at f,e0000000/sbus at f,e0001000 at 2,0 SUNW,hme
Probing /iommu at f,e0000000/sbus at f,e0001000 at 3,0 Nothing there
Cpu #0 Ross,RT625
Cpu #1 Ross,RT625
Cpu #2 Ross,RT625
Cpu #3 Ross,RT625
Probing Memory Bank #0 64 Megabytes of DRAM
Probing Memory Bank #1 Nothing there
Probing Memory Bank #2 Nothing there
Probing Memory Bank #3 Nothing there
Probing Memory Bank #4 Nothing there
Probing Memory Bank #5 64 Megabytes of DRAM
Probing Memory Bank #6 Nothing there
Probing Memory Bank #7 8 Megabytes of VRAM
Probing /obio at 2,0 cgfourteen
Probing /iommu at f,e0000000/sbus at f,e0001000 at f,0 espdma esp sd st ledma le
SUNW
,bpp
Probing /iommu at f,e0000000/sbus at f,e0001000 at e,0 SUNW,DBRIe
Probing /iommu at f,e0000000/sbus at f,e0001000 at 0,0 Nothing there
Probing /iommu at f,e0000000/sbus at f,e0001000 at 1,0 Nothing there
Probing /iommu at f,e0000000/sbus at f,e0001000 at 2,0 SUNW,hme
Probing /iommu at f,e0000000/sbus at f,e0001000 at 3,0 Nothing there
Panic Info:
panic[cpu3]/thread=f60c4520: BAD TRAP: type=9 (Data fault) rp=fbfbe75c
addr=e6c0
0360 mmu_fsr=1a6 rw=2 occurred in module "unix" due to an illegal access to
a us
er address
pkginstall: Data fault
kernel write fault at addr=0xe6c00360, pme=0x0
MMU sfsr=1a6: Invalid Address on supv data store at level 1
pte addr = 0xf6a00398, level = 1
pid=3156, pc=0xf00625c4, sp=0xfbfbe7a8, psr=0x1e9010c6, context=8
g1-g7: 0, f60ea28e, ffffffff, 62, f60c2d98, f0041000, f60c4520
fbfbe5d8 unix:die+b8 (9, f024ca84, f024c8c4, 1a6, 2, 1a6)
%l0-7: fbfbe75c e6c00360 fbfbe75c 00000010 00000000 000695d5 00000000
00000000
fbfbe658 unix:trap+790 (0, 1, f0000000, f5ee9750, f60c2d98, 0)
%l0-7: 00000000 00000000 fbfbe75c 00000009 000001a6 00000002 00000000
00000000
fbfbe700 unix:fault+84 (e6c00360, fbfbe8f8, 16, 3384d, 0, 62)
%l0-7: 1e9010c6 f00625c4 f00625c8 00002000 00000009 00000040 00000007
fbfbe700
fbfbe7a8 genunix:dnlc_lookup+118 (f590a108, e6c00360, 16, f590a100,
f6155610, 1)
%l0-7: f5d38f0c 00006100 fbfbe8f8 f6c07748 00000000 f60c4520 f0250648
fbfbeb80
fbfbe808 ufs:ufs_lookup+54 (f6c07748, f5a36f68, f6c076c0, 0, fbfbe8f8,
fbfbe8f4)
%l0-7: f5b1242c 00000000 f5a36f68 f6c00360 fbfbea48 00000000 f5cabe00
f6c07748
fbfbe870 genunix:lookuppnvp+2b4 (fbfbeb08, 0, f0277a5c, f02755f8, 1, 0)
%l0-7: f5b15904 00000000 f5a36f68 00000000 fbfbeb08 00000000 f5cabe00
f6c07748
fbfbe9f8 genunix:lookuppn+100 (f5ee9750, f5cabe00, f5cabe00, 0, fbfbeb7c, 0)
%l0-7: 00000001 fbfbeb08 00000000 00000000 00000000 00000000 00000000
00000000
fbfbea60 genunix:lookupname+e0 (808f3, 0, 1, 0, fbfbeb7c, 1)
%l0-7: 00000000 00000000 00000000 00000000 00000000 00000000 00000000
00000000
fbfbeb18 genunix:statvfs+14 (808f3, 54558, ef5fc6d0, 4, 8ed58, 607f4)
%l0-7: 1e001084 ef5db86c ef5db870 f0064800 00000062 f60c4520 f0250648
fbfbeb80
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