[Sunhelp] Mhz rating for chip?

[james]

On Sat, 11 Dec 1999, Gregory Leblanc wrote:

> So what are the architectural differences between the MicroSPARC chips used
> in the SS4/5 and the SuperSPARCs in the SS10/20?  I had thought that the
> SuperSPARCs were faster clock for clock than the MicroSPARCs, and if they
> are, why did they put MicroSPARCs in the SS4/5?

The short, simple explanation:

SuperSPARC is fairly similar to the Intel Pentium in memory interfacing.
It has a low overhead on cache hits, a high overhead on cache misses, and
a fairly high cache hit rate when equipped with SuperCache.  It is capable
of up to 3-way issue.

microSPARC and microSPARC-II are much different.  They rely on a fast
memory system with small caches.  They have a low overhead on cache hits
and a fairly low overhead on cache misses, but a poor cache hit rate.
They are capable of 2-way issue.

Both use physically indexed and tagged caches IIRC (much more of an issue
on SuperSPARC due to the larger cache sizes).  The HyperSPARC modules use
virtual caches which take more of a hit under heavy context switching.

SuperSPARC esp with SuperCache made for a combination that could perform
well in SMP mode (less memory bandwidth needed).  microSPARC was cheap to
manufacture and was an excellent performer for the price.  Remember, the
SS5 (and the SS4 even more so) were designed to address the bottom end of
the workstation market, similar to what the Ultra 5 does now.
SuperSPARC based systems (all the way up to the CS6400!) were designed
for the middle to high end.  The comparison doesn't hold for any attribute
other than price and intended purpose, but an analog would be the Intel
Celeron vs. Pentium-III.

Note that for very large cache-busting applications (Verilog circuit
simulation comes to mind) the microSPARC memory architecture will actually
outperform the SuperSPARC one.  For "typical" use a SS20/61 is
considerably faster than a SS5/110, but if your cache hit rate drops far
enough the SS5 will come out on top.

-James