[rescue] sparc10 cpu - what to do.

[Patrick Giagnocavo]

Isn't the Itanium the second or third time that Intel tried VLIW or
VLIW like architectures?

iAPX 432, up to 321 bits in length instructions

i860 with program-accessible pipelines

neither of these were total failures however for Intel, as the
superscalar expert cut his teeth on these two and this experience was
useful when he did the PentiumPRO chips; and the i860's graphics
register design experience were later re-purposed into SIMD-ish MMX
extensions for Pentium MMX.

My view: VLIW CPUs represent the ultimate in vendor lockin, given the
complexity of the compilers needed.

On Sun, Dec 18, 2016 at 10:57 AM, Jonathan Patschke <jp at celestrion.net> wrote:
> On Fri, 16 Dec 2016, Sandwich Maker wrote:
>
>> " Intel's thrown in the towel on Itanic.
>>
>> i'm not sure it was ever more than a science project for a customer to
>> intel; their own focus was always on their cash cow x86/x64.
>
>
> Ahem.
>
> i386 / amd64.
>
> Itanium was touted as the real any only way forward by Intel until AMD
> extended the i386 instruction ABI to 64 bits.  Rather regrettable that AMD
> did that, as IA64 threw away a lot of the things that make i386 so
> problematic.
>
> Unfortunately, it brought its own massive complications with it.  Remember
> when Intel basically said all of Itanium's performance issues would be
> solved by SGI because only they apparently had smart-enough compiler folks
> to write software that would use the VLIW model effectively?
>
> AMD tried to save themselves and accidentally gave Intel an easy way out
> when that never came to pass.
>
> --
> Jonathan Patschke
> Austin, TX
> USA
>
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