[rescue] sparc10 cpu - what to do.

[Patrick Giagnocavo]

My personal opinion: what helped to kill SPARC was interpreted
languages like Perl, where the code to be executed was far larger than
could fit in cache.

When running a compiled program, the smaller caches of SPARC didn't
matter as much. But with Perl, Python etc. having such a large
footprint, the x86 CPUs with more L2 cache gained an advantage.

Not sure if anyone agrees with that? It is my naive, non-OS-developer viewpoint.

On Fri, Dec 16, 2016 at 12:14 PM, Liam Proven <lproven at gmail.com> wrote:
> On 16 December 2016 at 18:42, Dave McGuire <mcguire at neurotica.com> wrote:
>>   The 80486 is little more than an 80386 with an 80387 on-chip.  There
>> are other differences, but that's the main one.
>
>
> No, hang on, that is not accurate or fair.
>
> The 386 is a simple, scalar 32-bit CPU.
>
> The 486 is pipelined -- it delivered roughly twice the
> instructions-per-clock of the 80386 -- as well as having on-board L1
> cache.
>
> It was a lot more than a 386+387 on the same die, although the ISA was
> near identical.
>
> The original P5 Pentium is superscalar -- it has 2 instruction
> pipelines and can sometimes do >1 IPC. It has branch prediction and
> speculative execution. And with clever coding and instruction
> sequencing, as id Software's John Carmack discovered, you can overlap
> integer and FPU instructions on the P5 and get a sustained 2
> instructions per clock /above/ the normal speed.
>
> The Pentium Pro has instruction decomposition and reordering.
>
> --
> Liam Proven b" Profile: https://about.me/liamproven
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