[rescue] SPARC memory query

[Francisco Javier Mesa-Martinez]

On Thu, 28 Nov 2002, Dave McGuire wrote:

> On Thursday, November 28, 2002, at 02:57 PM, Jochen Kunz wrote:
> >> I would have thought synchronous memory would have far greater
> >> burst transfer rates..
> > Burst transfer rates yes, but still high latency. The question is how
> > high the sustrained data transfer rate for linear and random access is.
> > Even with modern SDRAMs you can get over 120 ns latency time (with
> > cache
> > and chip set overhead) in case of cache and page miss. The DRAM cell
> > technic didn't get that much faster in the last years. Only the
> > interface type and speed has changed.
> >
> > That is the reason why the latest 3 GHz P4 can't keep up with a "real"
> > Sun, HP 9k, RS/6k, ... in data / IO intensive load. The CPU is waiting
> > for data most of the time. "Real Machines" have the memory and IO
> > bandwith to keep the CPU bussy.
>
>    The "balance" of a design is very, very important...this is something
> that the PeeCee industry can't quite seem to figure out.
>

The industry figured that out long time ago, they also figured out a few
other things like..."time to market", and  "economy of scale".....