[rescue] SMP on intel wasteful?

[dave at cca.org]

mcguire at neurotica.com writes:

>  This brings up an important (non-flamewar) point, however.  The
>current crop of modern microprocessors can considered to be
>"post-RISC", as processor architecture continues to evolve.  Indeed,
>the Alpha is considered by many to be a RISC architecture...but have
>you looked at the size of that instruction set?  There's nothing
>"R"educed about it.

As long as an arch is load/store and has fixed-length instructions,
I consider it RISC.

I'm intensely suspicious of the term "post-RISC". Most of the 
times I've seen it used, it was by people claiming that x86 is
"RISCy" simply because it uses superscalar/pipelining/out-of-order/etc
trickery that, of course, has nothing to do with "RISC".

I also consider VLIW to be RISC, though I don't consider Merced-whatever
to be VLIW.

And I consider the CDC-6600 to be RISC. :-)

>  Even the x86 architecure, while miraculously maintaining instruction
>set compatibility with previous implementations in spite of the fact
>that it was never designed to be scalable, incorporates many of the
>features that make RISC RISC, or that make post-RISC post-RISC.  The
>PPro for example (arguably Intel's only half-decent implementation of
>the x86 architecture) decomposes x86 instructions into "uops"
>(micro-operations) and then executes them in a processor core that
>very much resembles what we commonly refer to as RISC.

Too bad compilers can't optimize for the actual hardware, eh?
Every time I hear someone claiming such on-the-fly-translation
as being the Wave Of The Future, I wonder what performance would be
like if the compiler could actually see the micro engine.

------ David Fischer ------- dave at cca.org ------- http://www.cca.org ------
----- Being poked in the eye with a sharp stick makes baby jesus cry! -----