[rescue] SGI, MIPS, and IA-64

[dave at cca.org]

lefa at cats.ucsc.edu writes:

>The R10K can perform 2 Integer, 2 FP instructions plus one load/store in
>parallel. So it is able to schedule 5 instructions and retire 4 per clock
>cycle.

>All information about the R10K can be obtained from the horse's mouth:
>		
>http://www.sgi.com/processors/r10k/tech_info/

>The R10K is a beautiful design. 

Was that the one with seperate int/float caches, and cache-bypass 
instructions?

If that's the one I'm thinking of, it's design was influenced by the
influx of engineers from some supercomputer (or mini-super) company,
but I can't remember which... (Resulting in a chip which *screams*
on vector-oriented code.)

Or am I thinking of something else?

------ David Fischer ------- dave at cca.org ------- http://www.cca.org ------
----------------- Live each day like the Triffids are coming. -------------