[rescue] Re: Re: OH YEA??? [was: Re: Ultra?]

[Dave McGuire]

On August 4, Chris Hedemark wrote:
> >   40mhz vs. 270MHz is an important point, but let's also keep in mind
> > that this is an apples/oranges comparison.  With 1MB of cache, that
> > 40Mhz can actually do some serious work...while the 256K cache on the
> > U5's CPU is a joke.
> 
> Relevant excerpts from OpenBSD dmesg on U5 and SS10.  Just the facts,
> ma'am.
> 
> [U5]
> mainbus0 (root): SUNW,Ultra-5_10
> cpu0 at mainbus0: SUNW,UltraSPARC-IIi @ 333 MHz, version 0 FPU
> cpu0: physical 32K instruction (32 b/l), 16K data (32 b/l), 2048K
> external (64 b/l)
> 
> -vs-
> 
> [SS10]
> mainbus0 (root): SUNW,SPARCstation-10
> cpu0 at mainbus0: TMS390Z50 v0 or TMS390Z55 @ 50 MHz, on-chip FPU
> cpu0: physical 20K instruction (64 b/l), 16K data (32 b/l), 1024K
> external (32 b/l) cache enabled
> 
> Just wanna put that cache myth to rest.

  *sigh*

  And I suppose next you're going to tell us that ALL Ultra5s come in
this configuration.  Ultra5s with useful cache are by far the least
common and most expensive.  To follow your logic, I could say
something like "since there are SPARCstation-10 systems with 150MHz
processors, ALL SPARCstation-10 systems have 150MHz processors!"

  (Oh, and here comes the personal attack to which you've become
accustomed.  You seem to earn them frequently, I've noticed.  I wonder
why that might be.  Possibly because you're an asshole.)

  Why do you always have to be such an asshole?  Does it just come
naturally, or do you have to work at it?

       -Dave

-- 
Dave McGuire                     "I haven't worn pants in 14 months!"
St. Petersburg, FL                                   -Pete Wargo