[rescue] When it comes to cache - I want as much as possible!

[George Adkins]

On Sunday 11 November 2001 02:24 pm, you wrote:
> George,
>
> Granted this is a totally different arena (x86, not
> SPARC arch.), but I had occasion to try and re-purpose
> an old P90 box as a thin client running Linux on
> Friday. As I was trying to get through some hairy
> video problems, I disabled the 256K cache.
>
> It made a profound difference, *easily* 15-20%
> performance hit, just doing the install...
>
Sure, a 256K buffer backing the 16K L1 cache in a Pentium might well produce 
a 15-20% performance boost.  I can understand that.  
I would more accurately call that a low-performing, high-latency 256K L1 
cache, considering the lack of anything resembling space in the 'so-called L1 
cache' in the processor die.

128K of sram cache produced a 20-30% performance increase with the 
I486DX2-50's and -66's as well.  Consider that they had 8K of L1 cache, and 
were internally clock-doubled from their system bus speed.  it's easy to see 
how a tiny L2 cache buffer can make a huge difference in dealing with 
buffering Main Memory access, but that's about all they are good for.

If caches weren't important for other things, (things that require space, 
like context switching) then why does an SM71 (75Mhz/1M cache) kick the dog 
doo out of a Ross Hypersparc HS125/256 ???

And why are the BIG Alpha and UltraSparc procs equipped with 8Meg Caches?

George