[rescue] Solbourne 5/600 Diagnostic Codes

[Stephen Dowdy]

Zach,

	http://www.cs.colorado.edu/~dowdy/Solbourne/
specifically, 
	http://www.cs.colorado.edu/~dowdy/Solbourne/Parts-List.html
will help you ID your boards by partnumber

I've got pictures of many of the KBus and VME boards in their appropriate
sections if you need visual ID.

You wanna make sure that you have boards in the following positions.

Slot 7 (leftmost) contains I/O board.  (If Slot 7 is bad, Slot 6 can be
used, but if that's bad you're hosed)

Put the cpus in slots 2-6 separated by memory or other boards for cooling
purposes. (in a dual cpu config, i'd do slots 3 and 5 or 4 and 2)

If you have a CG30 video board, put it in slot6

Memory (for the most part) can go anywhere.


As for the diagnostic LEDs...

Diagnostic codes are of the form :

	_ _  |  PP  |  - -  |  S S   (cycling...)

Where "_ _" is a blank display
"PP" is a Primary ROM test number
" - - " is a separator dash
"SS" is a secondary/subsidiary code

As a general rule, you might find the low nibble of the Secondary code
reflects the slot number of a failing board.  I.E. in your case 'C4'
might indicate that slot 4 was where the error was detected.  This is not
always the case, however, but can often be used as a first try to locate
failed components. (i.e. if you move the board in slot 4 to slot3 and the
subsidiary error code becomes "C3", you can be pretty sure that board is
to blame)


Tests for the Series5 run from "00" through ??.

Usually, they run through 00..0F, 10..1F, 20..2F, 30..3F and then things go
real fast from there and vary somewhat.

If you really are going past 18 through 3F, then an A1 would be a very
high-level test, usually related to getting near the OS loader stages
(console selection, etc).  Test B6 IIRC, is a console detection/selection
phase.

If you have two cpus, usually one will assume MASTER status (either by
lowest slot or the ROM variable "MASTER" being an integer slot number).
Both CPUs run through tests upto somepoint in the 30s.  Once the Master is
selected, the slave(s) go into slave wait mode on the master finishing its
testing.  The slaves will report:

	_ _  |  S L  |  - -  |  N N

Where "SL" means slave, and "NN" is slot number of that board.

Once the Master CPU hits something like "5F" (can't recall), then each
slave will start a subset of the tests upto "5F" sequentially.  I have
rarely seen an MP configuration fail during a slave test once the sytem
goes MP in the ROM Tests.

What i would do...

	Install the following:

	I/O board in Slot 7
	Memory board in Slot 1
	CPU board in Slot 2
	*nothing else*

try that configuration.  If it fails, swap the cpu, try again.  if it
still fails, swap the memory (if you have another memory board).  If it
still fails, put the I/O board into slot6 and disconnect the VME leads
(the 3 50-pin flat-ribbon cables).  If it's still failing at this point,
its likely either the I/O board or the backplane, and you are pretty
much hosed.

If you get further, send me e-mail directly off-list.

--stephen
--
Stephen Dowdy - Systems Administrator - CS Dept - Univ of Colorado at Boulder
dowdy at cs.colorado.edu  --  http://www.cs.colorado.edu/~dowdy/signature.html