Re(2): [SunRescue] (no subject)

[Tim Hauber]

rescue at sunhelp.org writes:
>This is a popular misconception (the 9 chip requirement).  Some 3 chip
>SIMMs have marginal DRAM refresh timing and will have problems.  Most
>"quality" 3 chip RAM (Samsung/Hitachi/NEC/etc) works fine.
>
>Sun themselves shipped 3 chip 4MB SIMMs for the Sparc 2 and 4/600.  I'd
>take a barcoded 3 chip SIMM over a generic 9 chip any day.
>
>-James

here's a little scoop on 3 chip memory. most companies used 2 4bit  chips,
and a 1 bit parity chip (4+4+1 is 9) the problem shows up when the timing
of the oddball chip is different enough than the 4 bit chips that one of
them a) either doesn't refresh at all (cheap crap memory) or b) either
doesn't get the info ready quick enough, or doesn't hold it ready long
enough for the read cycle from the CPU c) the opposite of b on the write
cycle, b and c don't mean the memory is junk, they just mean the CPU and
memory don't have matching specs.  This style of SIMM can be seen by the
fact that there are two distinctly different styles of chip soldered on
them, sometimes even different physical size.

There are also 3 chip SIMMS with all identical chips on them, these should
be immune to timing problems (barring actual defects of course) I don't
know how these work, They must be either ignoring 3 bits (a waste) or
maybe somebody made 3 bit chips, just for parity SIMMS (which makes sense,
but that doesn't mean it happened)

I don't hear people grumbling about 72 pin SIMMS with oddball parity, but
there are 36 bit 72 Pin Simms built out of 2 16bit and 1 four bit chips,
which should have the same timing problems as the 3 chip 30 pin SIMMS.

Tim