[geeks] Sun-1 with Two CPUs?

[der Mouse]

> In Lecture 14 (at 52:00) of the Fall 2009 CS 61C course at UC
> Berkeley, Dr. Culler mentions that the implementation of the Motorola
> 68000's hardware page fault handling mechanism was defective to such
> a degree that a second "processor" was needed (running one
> instruction behind) in order to stash the PC of the instruction that
> caused the page fault so that it could be retrieved from the page
> fault handler.

That sounds...a little confused.

I don't think the 68000 _had_ page faults, because it didn't have an
MMU.  External MMUs were done, of course, but by the time the MMU gets
the faulting address, it's too late to do anything with the instruction
that's referencing memory except give it a memory bus fault, and that
is what had the problem.  (Memory bus faults in a non-MMU machine are
normally drastic enough that saving enough state to restart the
faulting instruction exactly is not necessary, after all.)

I don't think it was Sun who built the two-CPU machine with one
processor running one instruction behind the other, though; I thought
that was someone else (Masscomp maybe?).

> [...], using two of them in such a manner would be a bit silly (and
> difficult-to-impossible, when you take into consideration
> interactions with external state),

I'm not sure what they did about that.  I've heard of the two-CPU
machine from enough different sources by now that I believe it, but I
don't know details.  Offhand, I'd guess that the hardware saves bus
cycles from the leading processor in some kind of queue and replays
them to the lagging processor, thus providing it with the same
CPU-visible environment but without duplicating external effects such
as device register accesses.  After all, the queue doesn't need to be
more than one instruction's accesses deep.

> so I can only assume that this "processor" was a bit of custom
> hardware that noticed when the processor was in the instruction
> prefetch state and stashed the address somewhere [...]

The version I heard was that when the leading processor faults, the
processors switch roles and run with the other CPU leading until the
next bus fault.  If true, the processors must have been at least mostly
identical.

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