[geeks] Makefile question

[Greg A. Woods]

[ On Saturday, November 9, 2002 at 13:42:35 (-0500), Joshua D Boyd wrote: ]
> Subject: Re: [geeks] Makefile question
>
> On Sat, Nov 09, 2002 at 02:12:35AM -0600, Jonathan C Patschke wrote:
> 
> > OBJS = foo.o bar.o baz.o bot.o
> > 
> > Then:
> > foo.o: foo.cpp
> > 
> > bar.o: bar.cpp
> > 
> > baz.o: baz.cpp
> > 
> > bot.o: bat.cpp
> > 
> > Now, the steps for building each of your .o files, and your .a file are 
> > all separate, and gmake will know how to parallelize them.
> 
> So, there isn't some way to get around adding all those extra lines
> other than writing a script that builds the makefile?

Yup, there is.  Implicit rules and/or with GNU Make you can also use
static pattern rules.

With implict rules the source is implicitly a dependency of the target.

Make by default includes implicit rules for building *.o files from
either *.c or *.cpp files, so by default you don't need the explicit
"foo.o: foo.cpp" dependency declarations -- they are redundant.

Here's an example of a GNU Make static pattern rule direct from the GNU
Make manual:

     objects = foo.o bar.o
     
     all: $(objects)
     
     $(objects): %.o: %.c
             $(CC) -c $(CFLAGS) $< -o $@

You need only adjust it as desired for CPP.  (but first read about and
understand the implications of using GNU Make static pattern rules --
implicit rules are generic to all makes)

> Well I've converted it to your way for now.  In a day or two, if nothing
> else is suggested, I'll just break down and make a shell script to
> create the Makefile, either that or learn autoconf, etc.

Or just read the GNU Make manual.  :-)

GNU Automake really does make managing "GNU standard" makefiles a lot
easier though.

-- 
								Greg A. Woods

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