[geeks] T H E??b r i Q

[joshua d boyd]

On Thu, Jul 19, 2001 at 08:36:06PM -0400, dave at cca.org wrote:
> Someone told me that POWER (and probably PPC) started out a clean RISC,
> and they bolted an ugly CISC set of instructions onto the side, like CDC
> did with the 6600 way back when... can anyone confirm/deny? (I'm thinking
> specificly of memory-to-memory instructions.)

I certainly can't say much of anything about the POWER chips.

However, I'm fairly certain that nothing in the IBM PPC chips isn't also
in the Motorola PPC chips (which I say because come to think of it, I've
only fiddled with Motorola PPCs).  Actually, I take that back.  I heard
that after the G3 they agreed to no longer limit themselves to the exact
same feature set (hence why motorola has altivec and IBM doesn't).

So, we definately don't have register to memory, memory to register, or
memory to memory additions or subtractions.  Nope, there are no memory
access methods that would be called CISC like (except maybe in Altivec,
which I'm not familiar with). 

I don't know why I'm not crazy about PPCs.  The asm isn't that much
different from other RISC chips.  Plus, altivec is cool.

-- 
Joshua D. Boyd